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A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing

Lenart, Thomas LU ; Svensson, Henrik LU and Öwall, Viktor LU (2008) IEEE International Symposium on Electronic Design, Test & Applications (DELTA) In [Host publication title missing] p.398-404
Abstract
This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
398 - 404
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Electronic Design, Test & Applications (DELTA)
external identifiers
  • WOS:000254291500082
  • Scopus:50649103294
ISBN
978-0-7695-3110-6
DOI
10.1109/DELTA.2008.85
language
English
LU publication?
yes
id
556d90d1-8b26-46b4-8ff2-dda758d07f55 (old id 1160903)
date added to LUP
2008-08-21 13:46:27
date last changed
2017-01-01 08:03:21
@inproceedings{556d90d1-8b26-46b4-8ff2-dda758d07f55,
  abstract     = {This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.},
  author       = {Lenart, Thomas and Svensson, Henrik and Öwall, Viktor},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-0-7695-3110-6},
  language     = {eng},
  pages        = {398--404},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing},
  url          = {http://dx.doi.org/10.1109/DELTA.2008.85},
  year         = {2008},
}