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Reducing computational complexity of branch metric calculations in a trellis decoder

Rupanagudi, Sudhir Rao ; Rupanagudi, Vinita ; Kamuf, Matthias LU and Öwall, Viktor LU (2008) International Symposium on Wireless Personal Multimedia Communications (WPMC), 2008
Abstract
Trellis decoding is widely used, in this present day of communication and data storage, in a wide variety of applications such as decoding convolution codes, baseband detection for wireless

systems and also to detect recorded data. This is achieved by implementing the Viterbi algorithm. This paper presents various methodologies of reducing the computational complexity

of the branch metric unit in a trellis decoder. Further, a new methodology identified by us, which can be used to simplify the computations further, has been discussed. The adoption of

this method, has been verified in a 0.13μ standard CMOS process, which shows 60% reduction in area as compared to the designs incorporating the existing methodologies.
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Contribution to conference
publication status
published
subject
pages
4 pages
conference name
International Symposium on Wireless Personal Multimedia Communications (WPMC), 2008
conference location
Saariselkä, Finland
conference dates
2008-09-08 - 2008-09-11
language
English
LU publication?
yes
id
3dc0f7e3-b60f-4743-a3ab-eae3fa437c11 (old id 1218417)
date added to LUP
2016-04-04 12:53:45
date last changed
2018-11-21 21:11:17
@misc{3dc0f7e3-b60f-4743-a3ab-eae3fa437c11,
  abstract     = {{Trellis decoding is widely used, in this present day of communication and data storage, in a wide variety of applications such as decoding convolution codes, baseband detection for wireless<br/><br>
systems and also to detect recorded data. This is achieved by implementing the Viterbi algorithm. This paper presents various methodologies of reducing the computational complexity<br/><br>
of the branch metric unit in a trellis decoder. Further, a new methodology identified by us, which can be used to simplify the computations further, has been discussed. The adoption of<br/><br>
this method, has been verified in a 0.13μ standard CMOS process, which shows 60% reduction in area as compared to the designs incorporating the existing methodologies.}},
  author       = {{Rupanagudi, Sudhir Rao and Rupanagudi, Vinita and Kamuf, Matthias and Öwall, Viktor}},
  language     = {{eng}},
  title        = {{Reducing computational complexity of branch metric calculations in a trellis decoder}},
  year         = {{2008}},
}