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NoC-based CSP support for a Java chip multiprocessor

Gruian, Flavius LU orcid and Schoeberl, Martin (2010) NORCHIP Conference, 2010
Abstract
In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
NoC, CSP, multiprocessor, Java
host publication
[Host publication title missing]
pages
6 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
NORCHIP Conference, 2010
conference location
Tampere, Finland
conference dates
2010-11-15 - 2010-11-16
external identifiers
  • scopus:78751488984
ISBN
978-1-4244-8972-5
DOI
10.1109/NORCHIP.2010.5669484
language
English
LU publication?
yes
id
13d154d9-bc48-43a2-8b5d-a9ce0950383d (old id 1712463)
date added to LUP
2016-04-04 12:02:53
date last changed
2022-01-29 22:52:34
@inproceedings{13d154d9-bc48-43a2-8b5d-a9ce0950383d,
  abstract     = {{In this paper we examine the idea of implementing communicating sequential processes (CSP) constructs on a Java embedded chip multiprocessor (CMP). The approach is intended to reduce the memory bandwidth pressure on the shared memory, by employing a dedicated network-on-chip (NoC). The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. A CMP architecture of three processors is implemented and tested on an FPGA, showing a 15% increase in device area without performance penalties. Compared to shared memory-based communication, our NoC-based solution is between 2.3 and 11.5 times faster, depending on the communication and memory configuration.}},
  author       = {{Gruian, Flavius and Schoeberl, Martin}},
  booktitle    = {{[Host publication title missing]}},
  isbn         = {{978-1-4244-8972-5}},
  keywords     = {{NoC; CSP; multiprocessor; Java}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{NoC-based CSP support for a Java chip multiprocessor}},
  url          = {{http://dx.doi.org/10.1109/NORCHIP.2010.5669484}},
  doi          = {{10.1109/NORCHIP.2010.5669484}},
  year         = {{2010}},
}