Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

A coarse-grained dynamically reconfigurable architecture for digital signal processing

Zhang, Chenxin LU ; Thomas, Lenart ; Henrik, Svensson and Öwall, Viktor LU (2009) Swedish System-on-Chip Conference 2009 (SSoCC'09)
Abstract
This paper presents design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing the separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible static mapping of arbitrary applications, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality is demonstrated by mapping a radix 22 FFT processor reconfigurable between 32 and 1,024 points. Performance evaluation exhibits a great... (More)
This paper presents design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing the separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible static mapping of arbitrary applications, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality is demonstrated by mapping a radix 22 FFT processor reconfigurable between 32 and 1,024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to an ordinary DSP solution. (Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
DSP, CGRA
host publication
9th Swedish System-On-Chip Conference
pages
4 pages
publisher
Swedish Chapter of IEEE Solid-State Circuits Society (SSCS)
conference name
Swedish System-on-Chip Conference 2009 (SSoCC'09)
conference location
Arild, Sweden
conference dates
2009-05-04 - 2009-05-05
language
English
LU publication?
yes
id
0980879a-0467-4f62-aec1-2ee2a5be6f94 (old id 1405214)
date added to LUP
2016-04-04 11:22:29
date last changed
2025-04-04 15:02:56
@inproceedings{0980879a-0467-4f62-aec1-2ee2a5be6f94,
  abstract     = {{This paper presents design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing the separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible static mapping of arbitrary applications, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality is demonstrated by mapping a radix 22 FFT processor reconfigurable between 32 and 1,024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to an ordinary DSP solution.}},
  author       = {{Zhang, Chenxin and Thomas, Lenart and Henrik, Svensson and Öwall, Viktor}},
  booktitle    = {{9th Swedish System-On-Chip Conference}},
  keywords     = {{DSP; CGRA}},
  language     = {{eng}},
  publisher    = {{Swedish Chapter of IEEE Solid-State Circuits Society (SSCS)}},
  title        = {{A coarse-grained dynamically reconfigurable architecture for digital signal processing}},
  year         = {{2009}},
}