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Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding

Rodrigues, Joachim LU ; Akgun, OmerCan LU ; de la Calle, Adolfo; Acharya, Puneet; Leblebici, Yusuf and Öwall, Viktor LU (2010) 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009 In Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation 5953. p.347-356
Abstract
This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency the sub-threshold (sub-VT ) domain. The design is synthesized in 65nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4% in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
folding, energy model, sub-threshold, QRS detection, Cardiac pacemaker, wavelet filterbank, time-multiplexing
in
Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation
volume
5953
pages
347 - 356
publisher
Springer
conference name
19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009
external identifiers
  • wos:000278807700035
ISSN
0302-9743
1611-3349
project
Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers
language
English
LU publication?
yes
id
f8a30c5b-b93d-4b6d-915d-743dee8d2544 (old id 1444409)
date added to LUP
2009-08-03 13:49:33
date last changed
2018-05-29 09:51:17
@inproceedings{f8a30c5b-b93d-4b6d-915d-743dee8d2544,
  abstract     = {This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency the sub-threshold (sub-VT ) domain. The design is synthesized in 65nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4% in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.},
  author       = {Rodrigues, Joachim and Akgun, OmerCan and de la Calle, Adolfo and Acharya, Puneet and Leblebici, Yusuf and Öwall, Viktor},
  booktitle    = {Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation},
  issn         = {0302-9743},
  keyword      = {folding,energy model,sub-threshold,QRS detection,Cardiac pacemaker,wavelet filterbank,time-multiplexing},
  language     = {eng},
  pages        = {347--356},
  publisher    = {Springer},
  title        = {Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding},
  volume       = {5953},
  year         = {2010},
}