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A PLL based 12GHz LO generator with digital phase control in 90nm CMOS

Axholt, Andreas LU and Sjöland, Henrik LU (2009) Asia Pacific Microwave Conference, APMC 2009 In Proc. 2009 IEEE Asia Pacific Microwave Conference, APMC 2009, Singapore p.289-292
Abstract
A 12 GHz PLL with digital output phase control

has been implemented in a 90 nm CMOS process. It is intended

for LO signal generation in integrated phased array transceivers.

Locally placed PLLs eliminate the need of long high frequency

LO routing to each transceiver in a phased array circuit.

Routing losses are thereby reduced and design of integrated

phased array transceivers become more modular. A chip was

manufactured, featuring two separate fully integrated PLLs

operating at 12 GHz, with a common 1.5 GHz reference. The chip,

including pads, measures 1050x700 μm2. Each PLL consumes

15 mA from a 1.2 V supply, with a typical measured phase... (More)
A 12 GHz PLL with digital output phase control

has been implemented in a 90 nm CMOS process. It is intended

for LO signal generation in integrated phased array transceivers.

Locally placed PLLs eliminate the need of long high frequency

LO routing to each transceiver in a phased array circuit.

Routing losses are thereby reduced and design of integrated

phased array transceivers become more modular. A chip was

manufactured, featuring two separate fully integrated PLLs

operating at 12 GHz, with a common 1.5 GHz reference. The chip,

including pads, measures 1050x700 μm2. Each PLL consumes

15 mA from a 1.2 V supply, with a typical measured phase noise

of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds

360. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Phase locked loops, Beam steering, CMOS analog integrated circuits., Array signal processing, Millimeter wave antenna arrays
in
Proc. 2009 IEEE Asia Pacific Microwave Conference, APMC 2009, Singapore
pages
289 - 292
conference name
Asia Pacific Microwave Conference, APMC 2009
external identifiers
  • WOS:000279924300074
  • Scopus:77950688270
project
Analog/RF Circuits Group: Analog Building Blocks and Architectures
language
English
LU publication?
yes
id
6c1ec1af-c74d-469f-95a7-0432acb3291f (old id 1472781)
date added to LUP
2009-09-09 12:28:36
date last changed
2017-02-19 04:35:48
@inproceedings{6c1ec1af-c74d-469f-95a7-0432acb3291f,
  abstract     = {A 12 GHz PLL with digital output phase control<br/><br>
has been implemented in a 90 nm CMOS process. It is intended<br/><br>
for LO signal generation in integrated phased array transceivers.<br/><br>
Locally placed PLLs eliminate the need of long high frequency<br/><br>
LO routing to each transceiver in a phased array circuit.<br/><br>
Routing losses are thereby reduced and design of integrated<br/><br>
phased array transceivers become more modular. A chip was<br/><br>
manufactured, featuring two separate fully integrated PLLs<br/><br>
operating at 12 GHz, with a common 1.5 GHz reference. The chip,<br/><br>
including pads, measures 1050x700 μm2. Each PLL consumes<br/><br>
15 mA from a 1.2 V supply, with a typical measured phase noise<br/><br>
of -110 dBc/Hz at 1 MHz offset. The phase control range exceeds<br/><br>
360.},
  author       = {Axholt, Andreas and Sjöland, Henrik},
  booktitle    = {Proc. 2009 IEEE Asia Pacific Microwave Conference, APMC 2009, Singapore},
  keyword      = {Phase locked loops,Beam steering,CMOS analog
integrated circuits.,Array signal processing,Millimeter wave antenna
arrays},
  language     = {eng},
  pages        = {289--292},
  title        = {A PLL based 12GHz LO generator with digital phase control in 90nm CMOS},
  year         = {2009},
}