Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter

Dasalukunte, Deepak LU ; Ananthanarayanan, Karthik ; Kandasamy, Murali ; Rusek, Fredrik LU and Öwall, Viktor LU (2009) Norchip Conference, 2009
Abstract
This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory

(RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes

prohibitive when systems with large number of... (More)
This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory

(RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes

prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II

Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model. (Less)
Please use this url to cite or link to this publication:
author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
hardware implementation, faster-than-Nyquist, multicarrier, transmitter
host publication
[Host publication title missing]
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
Norchip Conference, 2009
conference location
Trondheim, Norway
conference dates
2009-11-16 - 2009-11-17
external identifiers
  • scopus:77949594500
ISBN
978-1-4244-4310-9
DOI
10.1109/NORCHP.2009.5397801
project
EIT_HSWC:Coding Coding, modulation, security and their implementation
language
English
LU publication?
yes
id
3ae1d9f4-16c4-44ac-847c-6d4e5bb62ec9 (old id 1497284)
date added to LUP
2016-04-04 12:00:29
date last changed
2022-03-31 19:19:29
@inproceedings{3ae1d9f4-16c4-44ac-847c-6d4e5bb62ec9,
  abstract     = {{This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory<br/><br>
(RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes<br/><br>
prohibitive when systems with large number of sub-carriers (&gt;64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II<br/><br>
Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.}},
  author       = {{Dasalukunte, Deepak and Ananthanarayanan, Karthik and Kandasamy, Murali and Rusek, Fredrik and Öwall, Viktor}},
  booktitle    = {{[Host publication title missing]}},
  isbn         = {{978-1-4244-4310-9}},
  keywords     = {{hardware implementation; faster-than-Nyquist; multicarrier; transmitter}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter}},
  url          = {{http://dx.doi.org/10.1109/NORCHP.2009.5397801}},
  doi          = {{10.1109/NORCHP.2009.5397801}},
  year         = {{2009}},
}