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A 5GHz 90-nm CMOS all digital phase-locked loop

Lu, Ping LU and Sjöland, Henrik LU (2009) IEEE Asian Solid-State Circuits Conference (ASSCC), 2009 p.65-68
Abstract
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
RF, Digitally Controlled Oscillator (DCO), Phase Locked Loop (PLL), All Digital Phase-Locked Loop (ADPLL), Time-to-Digital Converter (TDC), CMOS
pages
4 pages
conference name
IEEE Asian Solid-State Circuits Conference (ASSCC), 2009
external identifiers
  • scopus:76249114645
language
English
LU publication?
yes
id
67835061-470b-4506-b32c-0d9d5997cee8 (old id 1523016)
alternative location
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5357180&contentType=Conference+Publications&queryText%3DA+5GHz+90-nm+CMOS+all+digital+phase-locked+loop
date added to LUP
2010-01-04 11:54:51
date last changed
2017-01-01 08:11:36
@misc{67835061-470b-4506-b32c-0d9d5997cee8,
  abstract     = {An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.},
  author       = {Lu, Ping and Sjöland, Henrik},
  keyword      = {RF,Digitally Controlled Oscillator (DCO),Phase Locked Loop (PLL),All Digital Phase-Locked Loop (ADPLL),Time-to-Digital Converter (TDC),CMOS},
  language     = {eng},
  pages        = {65--68},
  title        = {A 5GHz 90-nm CMOS all digital phase-locked loop},
  year         = {2009},
}