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Bit-Serial CORDIC: Architecture and Implementation Improvements

Löfgren, Johan LU and Nilsson, Peter LU (2010) 2010 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2010) p.65-68
Abstract
Abstract in Undetermined
This paper presents a new and improved bit-serial CORDIC architecture. A detailed description of the bit-serial implementation and its Control Unit is presented. It is shown that the improvement is due to a reduction of registers in the implementation and is made possible by ensuring that the angular path is calculated prior to the corresponding vector paths. In addition, the improved architecture is implemented in VHDL and synthesized for a UMC 130 nm technology. With the chosen parameters, a word length of 12 bits and 8 stages in the CORDIC, it is shown that the improved architecture is 20 % smaller and consumes 26 % less power.
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
Midwest Symposium on Circuits and Systems Conference Proceedings
pages
65 - 68
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2010 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2010)
conference location
Seattle, Washington, United States
conference dates
2010-08-01
external identifiers
  • wos:000287099800017
  • scopus:77956607444
ISSN
1548-3746
1558-3899
ISBN
978-1-4244-7773-9
language
English
LU publication?
yes
id
36a32407-4a27-485a-b0fa-cf234e10f620 (old id 1600771)
date added to LUP
2016-04-01 10:34:02
date last changed
2025-01-14 18:00:25
@inproceedings{36a32407-4a27-485a-b0fa-cf234e10f620,
  abstract     = {{Abstract in Undetermined<br/>This paper presents a new and improved bit-serial CORDIC architecture. A detailed description of the bit-serial implementation and its Control Unit is presented. It is shown that the improvement is due to a reduction of registers in the implementation and is made possible by ensuring that the angular path is calculated prior to the corresponding vector paths. In addition, the improved architecture is implemented in VHDL and synthesized for a UMC 130 nm technology. With the chosen parameters, a word length of 12 bits and 8 stages in the CORDIC, it is shown that the improved architecture is 20 % smaller and consumes 26 % less power.}},
  author       = {{Löfgren, Johan and Nilsson, Peter}},
  booktitle    = {{Midwest Symposium on Circuits and Systems Conference Proceedings}},
  isbn         = {{978-1-4244-7773-9}},
  issn         = {{1548-3746}},
  language     = {{eng}},
  pages        = {{65--68}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Bit-Serial CORDIC: Architecture and Implementation Improvements}},
  year         = {{2010}},
}