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A 1.8V transmitter for 10/100 Mbps Ethernet physical layer

Tao, Cheng; Yang, Li; Li, Ning and Lu, Ping LU (2005) The 6th International Conference on ASIC, ASICON 2005 In [Host publication title missing] p.415-418
Abstract
A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
415 - 418
conference name
The 6th International Conference on ASIC, ASICON 2005
external identifiers
  • scopus:33847391266
ISBN
0-7803-9210-8
DOI
10.1109/ICASIC.2005.1611349
language
English
LU publication?
no
id
8833dcfd-73d0-4652-8709-b51759c789c1 (old id 1667568)
date added to LUP
2010-09-07 12:53:42
date last changed
2017-01-01 08:11:01
@inproceedings{8833dcfd-73d0-4652-8709-b51759c789c1,
  abstract     = {A 0.18 mum 1.8 V CMOS transmitter for 10/100Mbps Ethernet physical layer standards is described in this paper. The circuit is substantively a current-steering digital-to-analog converter with 5-bit resolution, 125MHz sample rate and 4ns transition time. A novel latch circuit is designed, as well as a structure is provided to realize the accurate rise/fall time control of waveform},
  author       = {Tao, Cheng and Yang, Li and Li, Ning and Lu, Ping},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7803-9210-8},
  language     = {eng},
  pages        = {415--418},
  title        = {A 1.8V transmitter for 10/100 Mbps Ethernet physical layer},
  url          = {http://dx.doi.org/10.1109/ICASIC.2005.1611349},
  year         = {2005},
}