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Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder

Dasalukunte, Deepak LU ; Rusek, Fredrik LU and Öwall, Viktor LU (2011) IEEE Computer Society Annual Symposium on VLSI In [Host publication title missing] p.296-300
Abstract
Architectural improvements for a multicarrier

faster-than-Nyquist (FTN) decoder are presented in this work.

A previously designed FTN decoder has been optimized during

implementation, especially with respect to memory considerations

to reduce area and power. The memory optimized architecture

achieves 28.7% savings in overall chip area and provides 43.8%

savings in the estimated power compared to the pre-optimized

design. The BER performance tradeoff from one of the memory

optimization shows that the degradation is acceptable and can

actually provide better performance for certain scenarios. The

other memory optimization considers the minimal... (More)
Architectural improvements for a multicarrier

faster-than-Nyquist (FTN) decoder are presented in this work.

A previously designed FTN decoder has been optimized during

implementation, especially with respect to memory considerations

to reduce area and power. The memory optimized architecture

achieves 28.7% savings in overall chip area and provides 43.8%

savings in the estimated power compared to the pre-optimized

design. The BER performance tradeoff from one of the memory

optimization shows that the degradation is acceptable and can

actually provide better performance for certain scenarios. The

other memory optimization considers the minimal buffering

required within the interference canceller, resulting in memory

reduction close to 50% of what was previously reported. The

performance from the actual RTL implementation of the FTN

decoder is also presented in comparison with the floating and

fixed point benchmark performances. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
faster-than-Nyquist, hardware implementation, optimization, iterative decoder
in
[Host publication title missing]
pages
5 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Computer Society Annual Symposium on VLSI
external identifiers
  • wos:000298386100050
  • scopus:80052602974
DOI
10.1109/ISVLSI.2011.7
project
EIT_HSWC:Coding Coding, modulation, security and their implementation
language
English
LU publication?
yes
id
5da425e2-4af3-4676-ab66-34c33f951109 (old id 1939753)
date added to LUP
2011-05-09 10:46:32
date last changed
2017-06-11 04:58:57
@inproceedings{5da425e2-4af3-4676-ab66-34c33f951109,
  abstract     = {Architectural improvements for a multicarrier<br/><br>
faster-than-Nyquist (FTN) decoder are presented in this work.<br/><br>
A previously designed FTN decoder has been optimized during<br/><br>
implementation, especially with respect to memory considerations<br/><br>
to reduce area and power. The memory optimized architecture<br/><br>
achieves 28.7% savings in overall chip area and provides 43.8%<br/><br>
savings in the estimated power compared to the pre-optimized<br/><br>
design. The BER performance tradeoff from one of the memory<br/><br>
optimization shows that the degradation is acceptable and can<br/><br>
actually provide better performance for certain scenarios. The<br/><br>
other memory optimization considers the minimal buffering<br/><br>
required within the interference canceller, resulting in memory<br/><br>
reduction close to 50% of what was previously reported. The<br/><br>
performance from the actual RTL implementation of the FTN<br/><br>
decoder is also presented in comparison with the floating and<br/><br>
fixed point benchmark performances.},
  author       = {Dasalukunte, Deepak and Rusek, Fredrik and Öwall, Viktor},
  booktitle    = {[Host publication title missing]},
  keyword      = {faster-than-Nyquist,hardware implementation,optimization,iterative decoder},
  language     = {eng},
  pages        = {296--300},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder},
  url          = {http://dx.doi.org/10.1109/ISVLSI.2011.7},
  year         = {2011},
}