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An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level

Nouripayam, Masoud LU ; Prieto, Arturo LU ; Kishorelal, Vignajeth Kuttuva and Rodrigues, Joachim LU (2021) p.1-4
Abstract
A non-von Neumann Near-Memory Computing architecture, optimized for CNN inference in edge computing, is integrated in the cache memory sub-system of a microcontroller unit. The NMC co-processor is evaluated using an 8-bit fixed-point quantized CNN model, and achieves an accuracy of 98% on the MNIST dataset. A full inference of the CNN model executed on the NMC processor, demonstrates an improvement of more than 34× in performance, and 28× in energy-efficiency, compared to the baseline scenario of a conventional single-core processor. The design achieves a performance of 1.39 GOPS (at 200 MHz) and an energy-efficiency of 49 GOPS/W, with negligible area overhead of less than 1%.
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
pages
1 - 4
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85124605226
ISBN
978-1-7281-9493-6
978-1-7281-8281-0
DOI
10.1109/ICECS53924.2021.9665530
language
English
LU publication?
yes
id
19bf38ed-55af-463b-8011-c2ed0a2ce15f
date added to LUP
2022-03-08 23:07:12
date last changed
2024-04-21 18:52:23
@inproceedings{19bf38ed-55af-463b-8011-c2ed0a2ce15f,
  abstract     = {{A non-von Neumann Near-Memory Computing architecture, optimized for CNN inference in edge computing, is integrated in the cache memory sub-system of a microcontroller unit. The NMC co-processor is evaluated using an 8-bit fixed-point quantized CNN model, and achieves an accuracy of 98% on the MNIST dataset. A full inference of the CNN model executed on the NMC processor, demonstrates an improvement of more than 34× in performance, and 28× in energy-efficiency, compared to the baseline scenario of a conventional single-core processor. The design achieves a performance of 1.39 GOPS (at 200 MHz) and an energy-efficiency of 49 GOPS/W, with negligible area overhead of less than 1%.}},
  author       = {{Nouripayam, Masoud and Prieto, Arturo and Kishorelal, Vignajeth Kuttuva and Rodrigues, Joachim}},
  booktitle    = {{2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)}},
  isbn         = {{978-1-7281-9493-6}},
  language     = {{eng}},
  pages        = {{1--4}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{An Energy-Efficient Near-Memory Computing Architecture for CNN Inference at Cache Level}},
  url          = {{http://dx.doi.org/10.1109/ICECS53924.2021.9665530}},
  doi          = {{10.1109/ICECS53924.2021.9665530}},
  year         = {{2021}},
}