Time-energy design space exploration for multi-layer memory architectures
Szymanek, Radoslaw LU ; Catthoor, F. and Kuchcinski, Krzysztof LU
(2004)
Proceedings. Design, Automation and Test in Europe Conference and Exhibition
p.318-323
- Abstract
- This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our algorithm is an application given as an annotated task graph and a specification of a multi-layer memory architecture. The algorithm produces Pareto trade-off points representing different multi-objective execution options for the whole application. Different metrics are used to estimate parameters for application-level Pareto points obtained by merging all Pareto diagrams of the tasks composing the application. We estimate application execution time although the final scheduling is not yet known. The algorithm makes it possible to trade off the... (More)
- This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our algorithm is an application given as an annotated task graph and a specification of a multi-layer memory architecture. The algorithm produces Pareto trade-off points representing different multi-objective execution options for the whole application. Different metrics are used to estimate parameters for application-level Pareto points obtained by merging all Pareto diagrams of the tasks composing the application. We estimate application execution time although the final scheduling is not yet known. The algorithm makes it possible to trade off the quality of the results and its runtime depending on the used metrics and the number of levels in the hierarchical composition of the tasks' Pareto points. We have evaluated our algorithm on a medical image processing application and randomly generated task graphs. We have shown that our algorithm can explore huge design space and obtain (near) optimal results in terms of Pareto diagram quality (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/613660
- author
- Szymanek, Radoslaw
LU
; Catthoor, F.
and Kuchcinski, Krzysztof
LU
- organization
- publishing date
- 2004
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- hierarchical composition, scheduling, Pareto diagrams, medical image processing application, multi-objective execution options, Pareto trade-off points, task graph, algorithm, parameterized memory architecture, energy consumption, execution time, exploration algorithm, multilayer memory architectures, time-energy design, space exploration
- host publication
- Proceedings. Design, Automation and Test in Europe Conference and Exhibition
- pages
- 318 - 323
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Proceedings. Design, Automation and Test in Europe Conference and Exhibition
- conference location
- Paris, France
- conference dates
- 2004-02-16 - 2004-02-20
- external identifiers
-
- wos:000189434000050
- scopus:3042656853
- ISBN
- 0-7695-2085-5
- DOI
- 10.1109/DATE.2004.1268867
- language
- English
- LU publication?
- yes
- id
- 20582792-bde9-46ee-94da-1bf1043f7406 (old id 613660)
- date added to LUP
- 2016-04-04 12:12:36
- date last changed
- 2022-02-06 08:30:08
@inproceedings{20582792-bde9-46ee-94da-1bf1043f7406,
abstract = {{This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. The input to our algorithm is an application given as an annotated task graph and a specification of a multi-layer memory architecture. The algorithm produces Pareto trade-off points representing different multi-objective execution options for the whole application. Different metrics are used to estimate parameters for application-level Pareto points obtained by merging all Pareto diagrams of the tasks composing the application. We estimate application execution time although the final scheduling is not yet known. The algorithm makes it possible to trade off the quality of the results and its runtime depending on the used metrics and the number of levels in the hierarchical composition of the tasks' Pareto points. We have evaluated our algorithm on a medical image processing application and randomly generated task graphs. We have shown that our algorithm can explore huge design space and obtain (near) optimal results in terms of Pareto diagram quality}},
author = {{Szymanek, Radoslaw and Catthoor, F. and Kuchcinski, Krzysztof}},
booktitle = {{Proceedings. Design, Automation and Test in Europe Conference and Exhibition}},
isbn = {{0-7695-2085-5}},
keywords = {{hierarchical composition; scheduling; Pareto diagrams; medical image processing application; multi-objective execution options; Pareto trade-off points; task graph; algorithm; parameterized memory architecture; energy consumption; execution time; exploration algorithm; multilayer memory architectures; time-energy design; space exploration}},
language = {{eng}},
pages = {{318--323}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Time-energy design space exploration for multi-layer memory architectures}},
url = {{http://dx.doi.org/10.1109/DATE.2004.1268867}},
doi = {{10.1109/DATE.2004.1268867}},
year = {{2004}},
}