Implementation of an area efficient crypto processor for a NB-IoT SoC platform
Cavo, Luis ; Fuhrmann, Sebastien and Liu, Liang LU
(2018)
4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018
- Abstract
This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has... (More)
This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.
(Less)
- author
- Cavo, Luis
; Fuhrmann, Sebastien
and Liu, Liang
LU
- organization
- publishing date
- 2018-12-11
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- host publication
- 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018 : NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings - NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings
- editor
- Nurmi, Jari ; Ellervee, Peeter ; Mihhailov, Juri ; Tammemae, Kalle and Jenihhin, Maksim
- article number
- 8573517
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 4th IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip, SoC 2018
- conference location
- Tallinn, Estonia
- conference dates
- 2018-10-30 - 2018-10-31
- external identifiers
-
- scopus:85060600733
- ISBN
- 9781538676561
- DOI
- 10.1109/NORCHIP.2018.8573517
- language
- English
- LU publication?
- yes
- id
- 20cfc0d4-ae32-4945-9e44-3d4f2897dec8
- date added to LUP
- 2019-02-08 11:59:20
- date last changed
- 2024-01-30 09:56:15
@inproceedings{20cfc0d4-ae32-4945-9e44-3d4f2897dec8,
abstract = {{<p>This paper presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) specifications for Long Term Evolution (LTE). The proposed processor has been adapted to the needs of the low end portfolio technologies that compose the Internet of Things (IoT) market, which addresses low-Area, low-cost and low-data rate applications. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a CPU in a cycle accurate virtual platform. Various architectural optimizations are proposed in order to achieve a reduction of area ranging from 5% to 42% in comparison to similar work. In a 65-nm CMOS technology, the processor has a size of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.</p>}},
author = {{Cavo, Luis and Fuhrmann, Sebastien and Liu, Liang}},
booktitle = {{2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018 : NORCHIP and International Symposium of System-on-Chip, SoC 2018 - Proceedings}},
editor = {{Nurmi, Jari and Ellervee, Peeter and Mihhailov, Juri and Tammemae, Kalle and Jenihhin, Maksim}},
isbn = {{9781538676561}},
language = {{eng}},
month = {{12}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Implementation of an area efficient crypto processor for a NB-IoT SoC platform}},
url = {{http://dx.doi.org/10.1109/NORCHIP.2018.8573517}},
doi = {{10.1109/NORCHIP.2018.8573517}},
year = {{2018}},
}