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A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

Axholt, Andreas LU and Sjöland, Henrik LU (2011) Asia Pacific Microwave Conference
Abstract
This paper presents a fully integrated 60 GHz frontend

for phased array receivers. For the first time in the literature

a phase controlled phased locked loop (PC-PLL) is used for

beamforming at 60 GHz. The front-end performs a two stage

frequency down-conversion, first from 60 GHz to 20 GHz, then

from 20 GHz to quadrature baseband. Both the local oscillator

signals at 20 GHz and 40 GHz are generated by a single 20 GHz

QVCO without any frequency multipliers. The measured results

show an input return loss better than -10 dB between 57.5 GHz

and 60.8 GHz, 15 dB voltage gain, and 9 dB noise figure. Twotone

measurements show a -12.5 dBm IIP3, 29 dBm IIP2,... (More)
This paper presents a fully integrated 60 GHz frontend

for phased array receivers. For the first time in the literature

a phase controlled phased locked loop (PC-PLL) is used for

beamforming at 60 GHz. The front-end performs a two stage

frequency down-conversion, first from 60 GHz to 20 GHz, then

from 20 GHz to quadrature baseband. Both the local oscillator

signals at 20 GHz and 40 GHz are generated by a single 20 GHz

QVCO without any frequency multipliers. The measured results

show an input return loss better than -10 dB between 57.5 GHz

and 60.8 GHz, 15 dB voltage gain, and 9 dB noise figure. Twotone

measurements show a -12.5 dBm IIP3, 29 dBm IIP2, and

-24 dBm ICP1dB. The phase control of the PLL has a resolution

of 3.2 degrees and the control range exceeds 360 degrees. The

chip consumes 80 mA from a 1.2 V supply, and measures 1400um

x 660um (900um x 500um excl. pads) incl. LNA, mixers, and

PC-PLL in a 90 nm RF CMOS process. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
in press
subject
pages
4 pages
conference name
Asia Pacific Microwave Conference
project
EIT_HSWC:RFNano RF tranceivers and nano devices
language
English
LU publication?
yes
id
8ec0f5aa-ce2c-4874-85e8-96ba25793ba5 (old id 2167896)
date added to LUP
2011-10-03 14:51:15
date last changed
2016-04-16 12:14:09
@misc{8ec0f5aa-ce2c-4874-85e8-96ba25793ba5,
  abstract     = {This paper presents a fully integrated 60 GHz frontend<br/><br>
for phased array receivers. For the first time in the literature<br/><br>
a phase controlled phased locked loop (PC-PLL) is used for<br/><br>
beamforming at 60 GHz. The front-end performs a two stage<br/><br>
frequency down-conversion, first from 60 GHz to 20 GHz, then<br/><br>
from 20 GHz to quadrature baseband. Both the local oscillator<br/><br>
signals at 20 GHz and 40 GHz are generated by a single 20 GHz<br/><br>
QVCO without any frequency multipliers. The measured results<br/><br>
show an input return loss better than -10 dB between 57.5 GHz<br/><br>
and 60.8 GHz, 15 dB voltage gain, and 9 dB noise figure. Twotone<br/><br>
measurements show a -12.5 dBm IIP3, 29 dBm IIP2, and<br/><br>
-24 dBm ICP1dB. The phase control of the PLL has a resolution<br/><br>
of 3.2 degrees and the control range exceeds 360 degrees. The<br/><br>
chip consumes 80 mA from a 1.2 V supply, and measures 1400um<br/><br>
x 660um (900um x 500um excl. pads) incl. LNA, mixers, and<br/><br>
PC-PLL in a 90 nm RF CMOS process.},
  author       = {Axholt, Andreas and Sjöland, Henrik},
  language     = {eng},
  pages        = {4},
  title        = {A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays},
  year         = {2011},
}