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Access Time Analysis for IEEE P1687

Ghani Zadegan, Farrokh LU ; Ingelsson, Urban; Carlsson, Gunnar and Larsson, Erik LU (2012) In IEEE Transactions on Computers 61(10). p.1459-1472
Abstract
The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan-path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e. concurrent schedule and sequential schedule. In the analysis, two types... (More)
The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan-path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e. concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e. network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Transactions on Computers
volume
61
issue
10
pages
1459 - 1472
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000307788900008
  • scopus:84865700036
ISSN
0018-9340
DOI
10.1109/TC.2011.155
language
English
LU publication?
no
id
d30c6726-a828-4fec-8fe6-25d69ae3a24c (old id 2340783)
date added to LUP
2012-02-10 14:02:33
date last changed
2017-07-30 04:54:00
@article{d30c6726-a828-4fec-8fe6-25d69ae3a24c,
  abstract     = {The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan-path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e. concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e. network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.},
  author       = {Ghani Zadegan, Farrokh and Ingelsson, Urban and Carlsson, Gunnar and Larsson, Erik},
  issn         = {0018-9340},
  language     = {eng},
  number       = {10},
  pages        = {1459--1472},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Computers},
  title        = {Access Time Analysis for IEEE P1687},
  url          = {http://dx.doi.org/10.1109/TC.2011.155},
  volume       = {61},
  year         = {2012},
}