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Design Automation for IEEE P1687

Ghani Zadegan, Farrokh LU ; Ingelsson, Urban; Carlsson, Gunnar and Larsson, Erik LU (2011) Design, Automation and Test in Europe (DATE 2011), In 2011 Design, Automation & Test in Europe
Abstract
The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total... (More)
The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time. (Less)
Please use this url to cite or link to this publication:
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publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2011 Design, Automation & Test in Europe
conference name
Design, Automation and Test in Europe (DATE 2011),
external identifiers
  • scopus:79957539188
ISBN
978-1-61284-208-0
DOI
10.1109/DATE.2011.5763228
language
English
LU publication?
no
id
63d89989-74cc-4b70-a895-6e803ac14e0e (old id 2340806)
date added to LUP
2012-02-10 14:01:57
date last changed
2017-08-27 06:15:18
@inproceedings{63d89989-74cc-4b70-a895-6e803ac14e0e,
  abstract     = {The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.},
  author       = {Ghani Zadegan, Farrokh and Ingelsson, Urban and Carlsson, Gunnar and Larsson, Erik},
  booktitle    = {2011 Design, Automation & Test in Europe},
  isbn         = {978-1-61284-208-0},
  language     = {eng},
  title        = {Design Automation for IEEE P1687},
  url          = {http://dx.doi.org/10.1109/DATE.2011.5763228},
  year         = {2011},
}