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Test Time Analysis for IEEE P1687

Ghani Zadegan, Farrokh LU ; Ingelsson, Urban; Carlsson, Gunnar and Larsson, Erik LU (2010) 19th IEEE Asian Test Symposium (ATS10) In Test Symposium (ATS), 2010 19th IEEE Asian p.455-460
Abstract
The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and... (More)
The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
Test Symposium (ATS), 2010 19th IEEE Asian
pages
6 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
19th IEEE Asian Test Symposium (ATS10)
external identifiers
  • scopus:79951601846
ISBN
978-1-4244-8841-4
language
English
LU publication?
no
id
ae929409-7759-4964-b827-ee5025e79895 (old id 2340875)
date added to LUP
2012-02-10 13:51:49
date last changed
2017-04-16 04:36:24
@inproceedings{ae929409-7759-4964-b827-ee5025e79895,
  abstract     = {The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.},
  author       = {Ghani Zadegan, Farrokh and Ingelsson, Urban and Carlsson, Gunnar and Larsson, Erik},
  booktitle    = {Test Symposium (ATS), 2010 19th IEEE Asian},
  isbn         = {978-1-4244-8841-4},
  language     = {eng},
  pages        = {455--460},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Test Time Analysis for IEEE P1687},
  year         = {2010},
}