Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
Vinay, N.S. ; Larsson, Erik LU
and Singh, Virendra
(2009)
DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340892
- author
- Vinay, N.S.
; Larsson, Erik
LU
and Singh, Virendra
- publishing date
- 2009
- type
- Contribution to conference
- publication status
- published
- subject
- conference name
- <em>DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes</em>
- conference location
- t, Nice, France
- conference dates
- 2009-04-20 - 2009-04-24
- language
- English
- LU publication?
- no
- id
- 4f60d110-0df3-4388-9958-8734a2fa7005 (old id 2340892)
- date added to LUP
- 2016-04-04 13:45:27
- date last changed
- 2018-11-21 21:16:04
@misc{4f60d110-0df3-4388-9958-8734a2fa7005,
author = {{Vinay, N.S. and Larsson, Erik and Singh, Virendra}},
language = {{eng}},
title = {{Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules}},
year = {{2009}},
}