Preemptive system-on-chip test scheduling
(2004) In IEICE Transactions on Information and Systems E87D(3). p.620-629- Abstract
- In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application... (More)
- In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340942
- author
- Larsson, Erik LU
- publishing date
- 2004
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- test scheduling, test access mechanism design, preemptive scheduling, system-on-chip testing
- in
- IEICE Transactions on Information and Systems
- volume
- E87D
- issue
- 3
- pages
- 620 - 629
- publisher
- The Institute of Electronics, Information and Communication Engineers
- external identifiers
-
- scopus:1642327140
- ISSN
- 0916-8532
- language
- English
- LU publication?
- no
- id
- 08c6daef-65b4-48c3-b705-ed5d8fc95d8b (old id 2340942)
- date added to LUP
- 2016-04-04 09:22:41
- date last changed
- 2022-01-29 17:33:07
@article{08c6daef-65b4-48c3-b705-ed5d8fc95d8b, abstract = {{In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.}}, author = {{Larsson, Erik}}, issn = {{0916-8532}}, keywords = {{test scheduling; test access mechanism design; preemptive scheduling; system-on-chip testing}}, language = {{eng}}, number = {{3}}, pages = {{620--629}}, publisher = {{The Institute of Electronics, Information and Communication Engineers}}, series = {{IEICE Transactions on Information and Systems}}, title = {{Preemptive system-on-chip test scheduling}}, volume = {{E87D}}, year = {{2004}}, }