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Efficient test solutions for core-based designs

Larsson, Erik LU ; Arvidsson, Klas; Fujiwara, H and Peng, Zebo (2004) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(5). p.758-775
Abstract
A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test... (More)
A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
scan-chain partitioning, system-on-chip (SOC) testing, test access mechanism design, test data transportation, test scheduling, test solutions
in
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
volume
23
issue
5
pages
758 - 775
publisher
Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:2542459381
ISSN
0278-0070
DOI
10.1109/TCAD.2004.826560
language
English
LU publication?
no
id
3c099580-3c66-4421-8b8a-1028a77f32c4 (old id 2340943)
alternative location
http://ieeexplore.ieee.org/iel5/43/28765/01291586.pdf
date added to LUP
2012-02-10 13:47:36
date last changed
2017-08-27 05:43:28
@article{3c099580-3c66-4421-8b8a-1028a77f32c4,
  abstract     = {A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system's test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost.},
  author       = {Larsson, Erik and Arvidsson, Klas and Fujiwara, H and Peng, Zebo},
  issn         = {0278-0070},
  keyword      = {scan-chain partitioning,system-on-chip (SOC) testing,test access mechanism design,test data transportation,test scheduling,test solutions},
  language     = {eng},
  number       = {5},
  pages        = {758--775},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title        = {Efficient test solutions for core-based designs},
  url          = {http://dx.doi.org/10.1109/TCAD.2004.826560},
  volume       = {23},
  year         = {2004},
}