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System-on-chip test scheduling with reconfigurable core wrappers

Larsson, Erik LU and Fujiwara, H (2006) In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14(3). p.305-309
Abstract
The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an... (More)
The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n), n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection testsre and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
preemptive scheduling, reconfigurable core wrapper, system-on-chip (SOC), test access mechanism (TAM) design, test scheduling, test time minimization
in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
volume
14
issue
3
pages
305 - 309
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:33646425889
ISSN
1063-8210
DOI
10.1109/TVLSI.2006.871757
language
English
LU publication?
no
id
0a5980ec-bbbd-41f3-a19c-5e5570f3121a (old id 2340952)
date added to LUP
2012-02-10 13:46:35
date last changed
2017-01-01 07:52:43
@article{0a5980ec-bbbd-41f3-a19c-5e5570f3121a,
  abstract     = {The problem with increasing test application time for testing core-based system-on-chip (SOC) designs is addressed with test architecture design and test scheduling. The scan-chains at each core are configured into a set of wrapper-chains, which by a core wrapper are connected to the test access mechanism (TAM), and the tests are scheduled in such a way that the test time is minimized. In this paper, we make use of reconfigurable core wrappers that, in contrast to standard wrappers, can dynamically change (reconfigure) the number of wrapper-chains during test application. We show that by using reconfigurable wrappers the test scheduling problem is equivalent to independent job scheduling on identical machines, and we make use of an existing preemptive scheduling algorithm that produces an optimal solution in linear time (O(n), n is the number of tests). We also show that the problem can be solved without preemption, and we extend the algorithm to handle: 1) test conflicts due to interconnection testsre and 2) cases when the test time of a core limits an optimal usage of the TAM. The overhead in logic is given by the number of configurations, and we show that the upper-bound is three configurations per core. We compare the proposed approach with the existing technique and show, in comparison, that our technique is 2% less from lower bound.},
  author       = {Larsson, Erik and Fujiwara, H},
  issn         = {1063-8210},
  keyword      = {preemptive scheduling,reconfigurable core wrapper,system-on-chip (SOC),test access mechanism (TAM) design,test scheduling,test time minimization},
  language     = {eng},
  number       = {3},
  pages        = {305--309},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  title        = {System-on-chip test scheduling with reconfigurable core wrappers},
  url          = {http://dx.doi.org/10.1109/TVLSI.2006.871757},
  volume       = {14},
  year         = {2006},
}