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An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment

Larsson, Erik LU (2008) In IET Computers and Digital Techniques 2(4). p.275-284
Abstract
The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time... (More)
The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed. Further, the proposed architecture efficiently tackles low throughput as the architecture allows multi-site testing at a constant ATE memory requirement, which is independent of the number of tested ICs. Advantages of the architecture, compared with test compression architecture, are that diagnostic capabilities are not reduced and there is no need for special handling of unknowns (X) in the produced test responses (PR). Experiments on ISCAS benchmark circuits and an industrial circuit have been performed. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
integrated circuits, testing, test data volume, compression, abort-on-fail
in
IET Computers and Digital Techniques
volume
2
issue
4
pages
275 - 284
publisher
Institution of Engineering and Technology
external identifiers
  • scopus:45849098719
ISSN
1751-8601
DOI
10.1049/iet-cdt:20070078
language
English
LU publication?
no
id
47ce2ca7-fa42-4f4d-ae91-3be28368acd8 (old id 2340968)
date added to LUP
2012-02-10 13:43:55
date last changed
2017-01-01 07:35:19
@article{47ce2ca7-fa42-4f4d-ae91-3be28368acd8,
  abstract     = {The semiconductor technology development makes it possible to fabricate increasingly advanced integrated circuits (ICs). However, because of imperfections at manufacturing, each individual IC must be tested. A major problem at IC manufacturing test is the increasing test data volume as it leads to high automatic test equipment (ATE) memory requirement, long test application time and low throughput. In contrast with existing approaches, which address either test data compression for ATE memory reduction or abort-on-fail testing for test time minimisation, an architecture that supports both test data compression and abort-on-fail testing at clock-cycle granularity is proposed, and hence both ATE memory reduction and test application time minimisation are addressed. Further, the proposed architecture efficiently tackles low throughput as the architecture allows multi-site testing at a constant ATE memory requirement, which is independent of the number of tested ICs. Advantages of the architecture, compared with test compression architecture, are that diagnostic capabilities are not reduced and there is no need for special handling of unknowns (X) in the produced test responses (PR). Experiments on ISCAS benchmark circuits and an industrial circuit have been performed.},
  author       = {Larsson, Erik},
  issn         = {1751-8601},
  keyword      = {integrated circuits,testing,test data volume,compression,abort-on-fail},
  language     = {eng},
  number       = {4},
  pages        = {275--284},
  publisher    = {Institution of Engineering and Technology},
  series       = {IET Computers and Digital Techniques},
  title        = {An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment},
  url          = {http://dx.doi.org/10.1049/iet-cdt:20070078},
  volume       = {2},
  year         = {2008},
}