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An Integrated System-On-Chip Test Framework

Larsson, Erik LU and Peng, Zebo (2001) Design, Automation and Test in Europe DATE Conference In [Host publication title missing] p.138-144
Abstract
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, system-on-chip, test access mechanism selection, test parallelization, test resource placement, power consumption, embedded systems
in
[Host publication title missing]
pages
138 - 144
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Design, Automation and Test in Europe DATE Conference
external identifiers
  • scopus:84893651091
ISSN
1530-1591
ISBN
0-7695-0993-2
DOI
10.1109/DATE.2001.915014
language
English
LU publication?
no
id
42e9e58d-1ebe-457e-ba48-ce9c3575bb78 (old id 2341098)
date added to LUP
2012-02-10 13:34:54
date last changed
2018-01-07 08:55:31
@inproceedings{42e9e58d-1ebe-457e-ba48-ce9c3575bb78,
  abstract     = {In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.},
  author       = {Larsson, Erik and Peng, Zebo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-0993-2},
  issn         = {1530-1591},
  keyword      = {testing,system-on-chip,test access mechanism selection,test parallelization,test resource placement,power consumption,embedded systems},
  language     = {eng},
  pages        = {138--144},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {An Integrated System-On-Chip Test Framework},
  url          = {http://dx.doi.org/10.1109/DATE.2001.915014},
  year         = {2001},
}