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An Integrated Framework for the Design and Optimization of SOC Test Solutions

Larsson, Erik LU and Peng, Zebo (2002) In Frontiers in Electronic Testing p.21-36
Abstract
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early... (More)
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
SOC, system-on-chip, test power consumption, test optimization
in
Frontiers in Electronic Testing
pages
21 - 36
publisher
Kluwer
external identifiers
  • scopus:0036693122
ISBN
1-4020-7205-8
language
English
LU publication?
no
id
57227dad-c37d-4316-a30e-905676f0513a (old id 2341119)
alternative location
http://www.ida.liu.se/labs/eslab/publications/pap/db/soc02.pdf
date added to LUP
2012-02-10 13:33:11
date last changed
2017-04-23 04:44:39
@inbook{57227dad-c37d-4316-a30e-905676f0513a,
  abstract     = {We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.},
  author       = {Larsson, Erik and Peng, Zebo},
  isbn         = {1-4020-7205-8},
  keyword      = {SOC,system-on-chip,test power consumption,test optimization},
  language     = {eng},
  pages        = {21--36},
  publisher    = {Kluwer},
  series       = {Frontiers in Electronic Testing},
  title        = {An Integrated Framework for the Design and Optimization of SOC Test Solutions},
  year         = {2002},
}