Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
(2011) 29th Norchip conference, 2011 p.1-4- Abstract
- Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain... (More)
- Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2438190
- author
- Meraji, Reza LU ; Anderson, John B LU ; Sjöland, Henrik LU and Öwall, Viktor LU
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 29th Norchip conference, 2011
- conference location
- Lund, Sweden
- conference dates
- 2011-11-14 - 2011-11-15
- external identifiers
-
- scopus:84863066798
- ISBN
- 978-1-4577-0514-4
- DOI
- 10.1109/NORCHP.2011.6126698
- language
- English
- LU publication?
- yes
- id
- 5e7d0e94-16a6-419d-8008-142130d96862 (old id 2438190)
- date added to LUP
- 2016-04-04 11:00:50
- date last changed
- 2024-01-12 22:46:59
@inproceedings{5e7d0e94-16a6-419d-8008-142130d96862, abstract = {{Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.}}, author = {{Meraji, Reza and Anderson, John B and Sjöland, Henrik and Öwall, Viktor}}, booktitle = {{[Host publication title missing]}}, isbn = {{978-1-4577-0514-4}}, language = {{eng}}, pages = {{1--4}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS}}, url = {{http://dx.doi.org/10.1109/NORCHP.2011.6126698}}, doi = {{10.1109/NORCHP.2011.6126698}}, year = {{2011}}, }