Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
(2011) Computer Design (ICCD), 2011 IEEE 29th International Conference on p.419-426- Abstract
- Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general purpose microprocessors.
In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify... (More) - Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general purpose microprocessors.
In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify policies and design low overhead hardware mechanisms to achieve this. Our work also introduces a new priority-based thread-scheduling algorithm for multiplexed architectures that improves multiplexed fault tolerant CMP throughput by prioritizing stalled threads.
Through simulation-based evaluation, we find that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient CMP architectures. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2733990
- author
- Subramanyan, Pramod ; Singh, Virendra ; Saluja, Kewal and Larsson, Erik LU
- organization
- publishing date
- 2011
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2011 IEEE 29th International Conference on Computer Design (ICCD)
- pages
- 8 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Computer Design (ICCD), 2011 IEEE 29th International Conference on
- conference location
- Amherst, MA, United States
- conference dates
- 2011-10-09 - 2011-10-12
- external identifiers
-
- scopus:83455219839
- ISSN
- 1063-6404
- ISBN
- 978-1-4577-1953-0
- DOI
- 10.1109/ICCD.2011.6081432
- language
- English
- LU publication?
- no
- id
- 6634b31f-af0a-4a14-a1a2-948b2f64c2ab (old id 2733990)
- date added to LUP
- 2016-04-01 13:23:41
- date last changed
- 2022-01-27 18:57:37
@inproceedings{6634b31f-af0a-4a14-a1a2-948b2f64c2ab, abstract = {{Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general purpose microprocessors.<br/><br> In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify policies and design low overhead hardware mechanisms to achieve this. Our work also introduces a new priority-based thread-scheduling algorithm for multiplexed architectures that improves multiplexed fault tolerant CMP throughput by prioritizing stalled threads.<br/><br> Through simulation-based evaluation, we find that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient CMP architectures.}}, author = {{Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal and Larsson, Erik}}, booktitle = {{2011 IEEE 29th International Conference on Computer Design (ICCD)}}, isbn = {{978-1-4577-1953-0}}, issn = {{1063-6404}}, language = {{eng}}, pages = {{419--426}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors}}, url = {{https://lup.lub.lu.se/search/files/3341672/2733993.pdf}}, doi = {{10.1109/ICCD.2011.6081432}}, year = {{2011}}, }