Advanced

Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors

Subramanyan, Pramod; Singh, Virendra; Saluja, Kewal and Larsson, Erik LU (2011) Computer Design (ICCD), 2011 IEEE 29th International Conference on In [Host publication title missing] p.419-426
Abstract
Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general­ purpose microprocessors.

In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify... (More)
Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general­ purpose microprocessors.

In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify policies and design low overhead hardware mechanisms to achieve this. Our work also introduces a new priority-based thread-scheduling algorithm for multiplexed architectures that improves multiplexed fault­ tolerant CMP throughput by prioritizing stalled threads.

Through simulation-based evaluation, we find that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient CMP architectures. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
8 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Computer Design (ICCD), 2011 IEEE 29th International Conference on
external identifiers
  • scopus:83455219839
ISSN
1063-6404
ISBN
978-1-4577-1953-0
DOI
10.1109/ICCD.2011.6081432
language
English
LU publication?
no
id
6634b31f-af0a-4a14-a1a2-948b2f64c2ab (old id 2733990)
date added to LUP
2012-06-07 14:56:28
date last changed
2017-01-01 05:38:45
@inproceedings{6634b31f-af0a-4a14-a1a2-948b2f64c2ab,
  abstract     = {Relentless scaling of CMOS fabrication technology has made contemporary integrated circuits increasingly susceptible to transient faults, wearout-related permanent faults, intermittent faults and process variations. Therefore, mechanisms to mitigate the effects of decreased reliability are expected to become essential components of future general­ purpose microprocessors.<br/><br>
In this paper, we introduce a new throughput-efficient architecture for multiplexed fault-tolerant chip multiprocessors (CMPs). Our proposal relies on the new technique of adaptive execution assistance, which dynamically varies instruction outcomes forwarded from the leading core to the trailing core based on measures of trailing core performance. We identify policies and design low overhead hardware mechanisms to achieve this. Our work also introduces a new priority-based thread-scheduling algorithm for multiplexed architectures that improves multiplexed fault­ tolerant CMP throughput by prioritizing stalled threads.<br/><br>
Through simulation-based evaluation, we find that our proposal delivers 17.2% higher throughput than perfect dual modular redundant (DMR) execution and outperforms previous proposals for throughput-efficient CMP architectures.},
  author       = {Subramanyan, Pramod and Singh, Virendra and Saluja, Kewal and Larsson, Erik},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-1-4577-1953-0},
  issn         = {1063-6404},
  language     = {eng},
  pages        = {419--426},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors},
  url          = {http://dx.doi.org/10.1109/ICCD.2011.6081432},
  year         = {2011},
}