TURNUS: a Design Exploration Framework for Dataflow System Design
(2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013- Abstract
- While research on the design of heterogeneous concurrent
systems has a long and rich history, a unified design methodology
and tool support has not emerged so far, and thus the creation
of such systems remains a difficult, time-consuming and error-prone
process. The absence of principled support for system evaluation and
optimization at high abstraction levels makes the quality of the resulting
implementation highly dependent on the experience or prejudices of the
designer. This is particularly critical when the combinatorial explosion
of design parameters overwhelms available optimization tools. In this
work we address these matters by presenting a unified... (More) - While research on the design of heterogeneous concurrent
systems has a long and rich history, a unified design methodology
and tool support has not emerged so far, and thus the creation
of such systems remains a difficult, time-consuming and error-prone
process. The absence of principled support for system evaluation and
optimization at high abstraction levels makes the quality of the resulting
implementation highly dependent on the experience or prejudices of the
designer. This is particularly critical when the combinatorial explosion
of design parameters overwhelms available optimization tools. In this
work we address these matters by presenting a unified design exploration
framework suitable for a wide range of different target platforms. The
design is unified and implemented at high level by using a standard
dataflow language, while the target platform is described using the IP-
XACT standard. This facilitates different design space heuristics that
guide the designer during validation and optimization stages without
requiring low-level implementations of parts of the application. Our
framework currently yields exploration and optimization results in terms
of application throughput and buffer size dimensioning, although other
co-exploration and optimization heuristics are available. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3408572
- author
- Brunet, Simone Casale ; Mattavelli, Marco and Janneck, Jörn LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- IEEE International Symposium on Circuits and Systems
- pages
- 1 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2013
- conference location
- Beijing, China
- conference dates
- 2013-05-19 - 2013-05-23
- external identifiers
-
- scopus:84883374799
- language
- English
- LU publication?
- yes
- id
- 279fcdb4-ed5a-4a8c-81f7-fe34032bb12d (old id 3408572)
- date added to LUP
- 2016-04-04 11:57:03
- date last changed
- 2022-03-23 18:20:48
@inproceedings{279fcdb4-ed5a-4a8c-81f7-fe34032bb12d,
abstract = {{While research on the design of heterogeneous concurrent<br/><br>
systems has a long and rich history, a unified design methodology<br/><br>
and tool support has not emerged so far, and thus the creation<br/><br>
of such systems remains a difficult, time-consuming and error-prone<br/><br>
process. The absence of principled support for system evaluation and<br/><br>
optimization at high abstraction levels makes the quality of the resulting<br/><br>
implementation highly dependent on the experience or prejudices of the<br/><br>
designer. This is particularly critical when the combinatorial explosion<br/><br>
of design parameters overwhelms available optimization tools. In this<br/><br>
work we address these matters by presenting a unified design exploration<br/><br>
framework suitable for a wide range of different target platforms. The<br/><br>
design is unified and implemented at high level by using a standard<br/><br>
dataflow language, while the target platform is described using the IP-<br/><br>
XACT standard. This facilitates different design space heuristics that<br/><br>
guide the designer during validation and optimization stages without<br/><br>
requiring low-level implementations of parts of the application. Our<br/><br>
framework currently yields exploration and optimization results in terms<br/><br>
of application throughput and buffer size dimensioning, although other<br/><br>
co-exploration and optimization heuristics are available.}},
author = {{Brunet, Simone Casale and Mattavelli, Marco and Janneck, Jörn}},
booktitle = {{IEEE International Symposium on Circuits and Systems}},
language = {{eng}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{TURNUS: a Design Exploration Framework for Dataflow System Design}},
url = {{https://lup.lub.lu.se/search/files/5892821/3408580.pdf}},
year = {{2013}},
}