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On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems

Löfgren, Johan LU and Nilsson, Peter LU (2011) 29th Norchip conference, 2011
Abstract
Abstract in Undetermined
This paper treats the hardware architecture and
implementation of mixed radix FFTs with cores of radix 3 and
radix 5 in addition to the standard radix 2 core. The implementation
flow graphs of the higher radix cores are presented
together with a description of how these cores afTect a pipelined
FFT implementation. It is shown that the mixed radix FFT is
more expensive than the radix 2 implementation - a mixed radix
FFT of 1200 points require 36 real multipliers in a pipelined
implementation whereas a 2048 radix 2 FFT needs 30 real
multipliers. However, half of the multipliers in the mixed radix
case can be constant. Therefore it is still feasible to use the... (More)
Abstract in Undetermined
This paper treats the hardware architecture and
implementation of mixed radix FFTs with cores of radix 3 and
radix 5 in addition to the standard radix 2 core. The implementation
flow graphs of the higher radix cores are presented
together with a description of how these cores afTect a pipelined
FFT implementation. It is shown that the mixed radix FFT is
more expensive than the radix 2 implementation - a mixed radix
FFT of 1200 points require 36 real multipliers in a pipelined
implementation whereas a 2048 radix 2 FFT needs 30 real
multipliers. However, half of the multipliers in the mixed radix
case can be constant. Therefore it is still feasible to use the mixed
radix FFT if an algorithm calls for it. (Less)
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publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
[Host publication title missing]
conference name
29th Norchip conference, 2011
conference location
Lund, Sweden
conference dates
2011-11-14 - 2011-11-15
external identifiers
  • scopus:84856914450
ISBN
978-1-4577-0514-4
DOI
10.1109/NORCHP.2011.6126703
language
English
LU publication?
yes
id
0d367803-510a-4e5d-beda-b028c1fbe409 (old id 2856180)
date added to LUP
2016-04-04 13:35:34
date last changed
2021-10-06 01:16:09
@inproceedings{0d367803-510a-4e5d-beda-b028c1fbe409,
  abstract     = {Abstract in Undetermined<br/>This paper treats the hardware architecture and<br/>implementation of mixed radix FFTs with cores of radix 3 and<br/>radix 5 in addition to the standard radix 2 core. The implementation<br/>flow graphs of the higher radix cores are presented<br/>together with a description of how these cores afTect a pipelined<br/>FFT implementation. It is shown that the mixed radix FFT is<br/>more expensive than the radix 2 implementation - a mixed radix<br/>FFT of 1200 points require 36 real multipliers in a pipelined<br/>implementation whereas a 2048 radix 2 FFT needs 30 real<br/>multipliers. However, half of the multipliers in the mixed radix<br/>case can be constant. Therefore it is still feasible to use the mixed<br/>radix FFT if an algorithm calls for it.},
  author       = {Löfgren, Johan and Nilsson, Peter},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-1-4577-0514-4},
  language     = {eng},
  title        = {On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems},
  url          = {http://dx.doi.org/10.1109/NORCHP.2011.6126703},
  doi          = {10.1109/NORCHP.2011.6126703},
  year         = {2011},
}