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A three bit second order audio band delta sigma modulator with 98.2dB SQNR

Felding, Henrik ; Hellman, Linus ; Tan, Siyu LU and Törmänen, Markus LU orcid (2016)
Abstract
A three bit second order delta sigma modulator for audio applications implemented in 130nm CMOS technology is presented. The modulator features two integrators, a flash quantizer and two current steering DACs. In order to minimize the effect of delays in the DACs, excessive loop delay (ELD) compensation is utilized. Using an oversampling ratio (OSR) of 80, the design consumes 2.8mW and achieves a simulated signal to quantization noise ratio (SQNR) of 98.2dB. The chip area is minimized by decreasing the number of digital to analog converters (DACs) by using the concept of partial integration. The compact design occupies an active core area of 630μm × 600μm.
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Delta Sigma modulation, Partial Integration, Excessive Loop Delay, Analogue to Digital conversion
host publication
2016 International Symposium on Integrated Circuits, ISIC 2016
article number
7829750
pages
4 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85013826361
ISBN
978-146739019-4
DOI
10.1109/ISICIR.2016.7829750
language
English
LU publication?
yes
id
2c34ddae-3e65-4038-9140-ffe7796b8146
date added to LUP
2017-01-02 10:57:15
date last changed
2022-03-08 23:41:30
@inproceedings{2c34ddae-3e65-4038-9140-ffe7796b8146,
  abstract     = {{A three bit second order delta sigma modulator for audio applications implemented in 130nm CMOS technology is presented. The modulator features two integrators, a flash quantizer and two current steering DACs. In order to minimize the effect of delays in the DACs, excessive loop delay (ELD) compensation is utilized. Using an oversampling ratio (OSR) of 80, the design consumes 2.8mW and achieves a simulated signal to quantization noise ratio (SQNR) of 98.2dB. The chip area is minimized by decreasing the number of digital to analog converters (DACs) by using the concept of partial integration. The compact design occupies an active core area of 630μm × 600μm.}},
  author       = {{Felding, Henrik and Hellman, Linus and Tan, Siyu and Törmänen, Markus}},
  booktitle    = {{2016 International Symposium on Integrated Circuits, ISIC 2016}},
  isbn         = {{978-146739019-4}},
  keywords     = {{Delta Sigma modulation; Partial Integration; Excessive Loop Delay; Analogue to Digital conversion}},
  language     = {{eng}},
  month        = {{12}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A three bit second order audio band delta sigma modulator with 98.2dB SQNR}},
  url          = {{http://dx.doi.org/10.1109/ISICIR.2016.7829750}},
  doi          = {{10.1109/ISICIR.2016.7829750}},
  year         = {{2016}},
}