Automatic local memory architecture generation for data reuse in custom data paths
Andersson, Per LU and Kuchcinski, Krzysztof LU
(2004)
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
p.137-144
- Abstract
- Traditional high level synthesis is able to yield high computational resource utilisation and short critical paths. The shortcomings of the generated designs usually lies in the memory architecture. To achieve good performance on a FPGA, the data must reside in the fast on-chip memories, but these are commonly too small for the data being processed. Traditional high level synthesis cannot cope with this situation. In this paper we present a technique for automatic generation of a memory architecture, data paths and associated controllers from a high level language such as C. Data reused during the processing are stored in a local memory, resulting in high performance even when the data are stored in shared off-chip memory. The technique is... (More)
- Traditional high level synthesis is able to yield high computational resource utilisation and short critical paths. The shortcomings of the generated designs usually lies in the memory architecture. To achieve good performance on a FPGA, the data must reside in the fast on-chip memories, but these are commonly too small for the data being processed. Traditional high level synthesis cannot cope with this situation. In this paper we present a technique for automatic generation of a memory architecture, data paths and associated controllers from a high level language such as C. Data reused during the processing are stored in a local memory, resulting in high performance even when the data are stored in shared off-chip memory. The technique is based on data dependence and data access pattern analysis. Commonly used data are duplicated in on-chip memory. High memory efficiency is achieved by rearranging the data memory layout during copying. We have applied our technique to typical signal analysis tasks. The results show that the data path does not need to stall waiting for data, even when all data are stored in a shared off-chip memory. The experiments have been carried ont on a Xilinx Virtex2 FPGA. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/614270
- author
- Andersson, Per
LU
and Kuchcinski, Krzysztof
LU
- organization
- publishing date
- 2004
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Custom data paths, Architecture generation, Automatic local memory, On-chip memories
- host publication
- Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
- pages
- 137 - 144
- publisher
- CSREA Press
- conference name
- Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04
- conference location
- Las Vegas, NV, United States
- conference dates
- 2004-07-21 - 2004-07-24
- external identifiers
-
- wos:000225880300019
- scopus:12744262154
- ISBN
- 1932415424
- language
- English
- LU publication?
- yes
- id
- 2e07af23-f137-4aa4-84ae-8ce6aa5fe2a7 (old id 614270)
- date added to LUP
- 2016-04-04 10:50:27
- date last changed
- 2022-01-29 20:53:13
@inproceedings{2e07af23-f137-4aa4-84ae-8ce6aa5fe2a7,
abstract = {{Traditional high level synthesis is able to yield high computational resource utilisation and short critical paths. The shortcomings of the generated designs usually lies in the memory architecture. To achieve good performance on a FPGA, the data must reside in the fast on-chip memories, but these are commonly too small for the data being processed. Traditional high level synthesis cannot cope with this situation. In this paper we present a technique for automatic generation of a memory architecture, data paths and associated controllers from a high level language such as C. Data reused during the processing are stored in a local memory, resulting in high performance even when the data are stored in shared off-chip memory. The technique is based on data dependence and data access pattern analysis. Commonly used data are duplicated in on-chip memory. High memory efficiency is achieved by rearranging the data memory layout during copying. We have applied our technique to typical signal analysis tasks. The results show that the data path does not need to stall waiting for data, even when all data are stored in a shared off-chip memory. The experiments have been carried ont on a Xilinx Virtex2 FPGA.}},
author = {{Andersson, Per and Kuchcinski, Krzysztof}},
booktitle = {{Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04}},
isbn = {{1932415424}},
keywords = {{Custom data paths; Architecture generation; Automatic local memory; On-chip memories}},
language = {{eng}},
pages = {{137--144}},
publisher = {{CSREA Press}},
title = {{Automatic local memory architecture generation for data reuse in custom data paths}},
year = {{2004}},
}