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Energy Efficient MIMO Channel Pre-processor Using a Low Complexity On-Line Update Scheme

Zhang, Chenxin LU ; Prabhu, Hemanth LU ; Liu, Liang LU ; Edfors, Ove LU and Öwall, Viktor LU (2012) Norchip conference, 2012 In [Host publication title missing]
Abstract
This paper presents a low-complexity energy efficient channel pre-processing update scheme, targeting the emerging 3GPP long term evolution advanced (LTE-A) downlink. Upon channel matrix renewals, the number of explicit QR decompositions (QRD) and channel matrix inversions are reduced since only the upper triangular matrices R and R^-1 are updated, based on an on-line update decision mechanism. The proposed channel pre-processing updater has been designed as a dedicated unit in a 65nm CMOS technology, resulting in a core area of 0.242mm2 (equivalent gate count of 116K). Running at a 330MHz clock, each QRD or R^-1 update consumes 4 or 2 times less energy compared to one exact state-of-the-art QRD in open literature.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Channel pre-processing, QR decomposition, MIMO, QR update
in
[Host publication title missing]
pages
4 pages
conference name
Norchip conference, 2012
external identifiers
  • scopus:84873549591
DOI
10.1109/NORCHP.2012.6403103
project
EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
HiPEC
language
English
LU publication?
yes
id
c38f7bdc-e5f5-4292-8d48-d09dd7dceed4 (old id 3128242)
date added to LUP
2012-10-11 16:26:40
date last changed
2017-04-16 04:32:21
@inproceedings{c38f7bdc-e5f5-4292-8d48-d09dd7dceed4,
  abstract     = {This paper presents a low-complexity energy efficient channel pre-processing update scheme, targeting the emerging 3GPP long term evolution advanced (LTE-A) downlink. Upon channel matrix renewals, the number of explicit QR decompositions (QRD) and channel matrix inversions are reduced since only the upper triangular matrices R and R^-1 are updated, based on an on-line update decision mechanism. The proposed channel pre-processing updater has been designed as a dedicated unit in a 65nm CMOS technology, resulting in a core area of 0.242mm2 (equivalent gate count of 116K). Running at a 330MHz clock, each QRD or R^-1 update consumes 4 or 2 times less energy compared to one exact state-of-the-art QRD in open literature.},
  author       = {Zhang, Chenxin and Prabhu, Hemanth and Liu, Liang and Edfors, Ove and Öwall, Viktor},
  booktitle    = {[Host publication title missing]},
  keyword      = {Channel pre-processing,QR decomposition,MIMO,QR update},
  language     = {eng},
  pages        = {4},
  title        = {Energy Efficient MIMO Channel Pre-processor Using a Low Complexity On-Line Update Scheme},
  url          = {http://dx.doi.org/10.1109/NORCHP.2012.6403103},
  year         = {2012},
}