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Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation

Winstead, Chris and Rodrigues, Joachim LU (2012) In IEEE Transactions on Circuits and Systems - II - Express Briefs 59(12). p.913-917
Abstract
echniques are evaluated for implementing error- correction codes (ECC) in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub- VT implementation is predicted to offer 29× gain in power consumption for a (3,6) LDPC decoder of length N = 512 operating at a throughput of 200Mbps, compared to standard digital implementation of the same design.
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Error correction codes, sub-threshold, ultra-low voltage, analog decoders, biomedical implants
in
IEEE Transactions on Circuits and Systems - II - Express Briefs
volume
59
issue
12
pages
913 - 917
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000314839100013
  • scopus:84873410214
ISSN
1558-3791
DOI
10.1109/TCSII.2012.2231040
language
English
LU publication?
yes
id
354ae55e-8dd9-4e85-9a9f-e87a5af6bf28 (old id 3130616)
date added to LUP
2012-10-18 14:03:21
date last changed
2017-01-01 03:53:01
@article{354ae55e-8dd9-4e85-9a9f-e87a5af6bf28,
  abstract     = {echniques are evaluated for implementing error- correction codes (ECC) in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub- VT implementation is predicted to offer 29× gain in power consumption for a (3,6) LDPC decoder of length N = 512 operating at a throughput of 200Mbps, compared to standard digital implementation of the same design.},
  author       = {Winstead, Chris and Rodrigues, Joachim},
  issn         = {1558-3791},
  keyword      = {Error correction codes,sub-threshold,ultra-low voltage,analog decoders,biomedical implants},
  language     = {eng},
  number       = {12},
  pages        = {913--917},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Circuits and Systems - II - Express Briefs},
  title        = {Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation},
  url          = {http://dx.doi.org/10.1109/TCSII.2012.2231040},
  volume       = {59},
  year         = {2012},
}