A 1.1-Gb/s 115-pJ/bit configurable MIMO detector using 0.13-um CMOS technology
(2010) In IEEE Transactions on Circuits and Systems II: Express Briefs 57(9). p.701-705- Abstract
- This brief presents an efficient and configurable multiple-input–multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 $times$ 2/3 $times$ 3/4 $times$ 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency,... (More)
- This brief presents an efficient and configurable multiple-input–multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 $times$ 2/3 $times$ 3/4 $times$ 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13- $muhbox{m}$ single-poly- and eight-metal (1P8M) CMOS technology with a core area of 3.9 $hbox{mm}^{2}$. Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40% more energy efficient than state of the art in the open literature. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1686585
- author
- Liu, Liang LU ; Ye, Fan ; Ma, Xiaojing ; Zhang, Tong and Ren, Junyan
- publishing date
- 2010
- type
- Contribution to journal
- publication status
- published
- subject
- in
- IEEE Transactions on Circuits and Systems II: Express Briefs
- volume
- 57
- issue
- 9
- pages
- 701 - 705
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:77956712458
- ISSN
- 1549-7747
- DOI
- 10.1109/TCSII.2010.2058494
- language
- English
- LU publication?
- no
- id
- 38eed877-cdc7-4574-ab15-9018b1770bcc (old id 1686585)
- date added to LUP
- 2016-04-04 08:56:44
- date last changed
- 2024-02-11 03:46:27
@article{38eed877-cdc7-4574-ab15-9018b1770bcc, abstract = {{This brief presents an efficient and configurable multiple-input–multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 $times$ 2/3 $times$ 3/4 $times$ 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13- $muhbox{m}$ single-poly- and eight-metal (1P8M) CMOS technology with a core area of 3.9 $hbox{mm}^{2}$. Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40% more energy efficient than state of the art in the open literature.}}, author = {{Liu, Liang and Ye, Fan and Ma, Xiaojing and Zhang, Tong and Ren, Junyan}}, issn = {{1549-7747}}, language = {{eng}}, number = {{9}}, pages = {{701--705}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Transactions on Circuits and Systems II: Express Briefs}}, title = {{A 1.1-Gb/s 115-pJ/bit configurable MIMO detector using 0.13-um CMOS technology}}, url = {{http://dx.doi.org/10.1109/TCSII.2010.2058494}}, doi = {{10.1109/TCSII.2010.2058494}}, volume = {{57}}, year = {{2010}}, }