A Fully Integrated 26dBm Linearized RF Power Amplifier in 65nm CMOS Technology
(2015) IEEE International Symposium on Circuits and Systems (ISCAS), 2015- Abstract
- In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA... (More)
- In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm 2 of chip area. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4937723
- author
- Ahmad, Waqas LU ; Xu, Leijun ; Törmänen, Markus LU and Sjöland, Henrik LU
- organization
- publishing date
- 2015
- type
- Contribution to conference
- publication status
- published
- subject
- pages
- 4 pages
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2015
- conference location
- Lisbon, Portugal
- conference dates
- 2015-05-24 - 2015-05-27
- external identifiers
-
- scopus:84946223529
- DOI
- 10.1109/ISCAS.2015.7168881
- project
- Distributed antenna systems for efficient wireless systems
- language
- English
- LU publication?
- yes
- id
- 3e2642fc-3a95-423d-85f3-3a43c57c64ee (old id 4937723)
- date added to LUP
- 2016-04-04 13:12:36
- date last changed
- 2024-01-13 06:19:20
@misc{3e2642fc-3a95-423d-85f3-3a43c57c64ee, abstract = {{In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm 2 of chip area.}}, author = {{Ahmad, Waqas and Xu, Leijun and Törmänen, Markus and Sjöland, Henrik}}, language = {{eng}}, title = {{A Fully Integrated 26dBm Linearized RF Power Amplifier in 65nm CMOS Technology}}, url = {{http://dx.doi.org/10.1109/ISCAS.2015.7168881}}, doi = {{10.1109/ISCAS.2015.7168881}}, year = {{2015}}, }