Partitioning and Optimization of High-Level Stream Applications for Multi-Clock-Domain Architectures
(2013) 2013 IEEE Workshop on Signal Processing Systems p.177-182- Abstract
- In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4076367
- author
- Brunet, Simone Casale ; Lausanne, Ecole ; Alberti, Claudio ; Mattavelli, Marco ; Amaldi, Eduardo and Janneck, Jörn LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2013 IEEE Workshop on Signal Processing Systems (SiPS 2013)
- pages
- 177 - 182
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2013 IEEE Workshop on Signal Processing Systems
- conference location
- Taipei, Taiwan
- conference dates
- 2013-10-16 - 2013-10-18
- external identifiers
-
- scopus:84896478442
- ISBN
- 9781467362368
- DOI
- 10.1109/SiPS.2013.6674501
- language
- English
- LU publication?
- yes
- id
- 6de16109-c98f-4089-b35b-35da9e62b7d9 (old id 4076367)
- date added to LUP
- 2016-04-04 14:23:32
- date last changed
- 2022-04-27 00:53:58
@inproceedings{6de16109-c98f-4089-b35b-35da9e62b7d9, abstract = {{In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder.}}, author = {{Brunet, Simone Casale and Lausanne, Ecole and Alberti, Claudio and Mattavelli, Marco and Amaldi, Eduardo and Janneck, Jörn}}, booktitle = {{2013 IEEE Workshop on Signal Processing Systems (SiPS 2013)}}, isbn = {{9781467362368}}, language = {{eng}}, pages = {{177--182}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Partitioning and Optimization of High-Level Stream Applications for Multi-Clock-Domain Architectures}}, url = {{http://dx.doi.org/10.1109/SiPS.2013.6674501}}, doi = {{10.1109/SiPS.2013.6674501}}, year = {{2013}}, }