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A low noise PLL based FM audio transmitter in 0.35 μm CMOS technology

Lu, Yan; Huo, Yiming; Wernehag, Johan LU and Sjöland, Henrik LU (2010) Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010 Asia In [Host publication title missing] p.202-205
Abstract
PLL (Phase Locked Loop) based frequency synthesizers are widely used in the wireless communication field. This paper puts focus on the design and implementation of a 60dB SNR (Signal to Noise Ratio) FM transmitter, which realizes direct frequency modulation of audio signal by utilizing a carrier frequency ranging from 78MHz to 108MHz, with a 100 kHz channel selection resolution. Fabricated in standard 0.35μm CMOS technology, this PLL's core circuit takes an area of 745×700 μm2. The transmitter has a total power consumption of below 56mW for a 3V supply, and the strongest measured spur is below -50dBc.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2010 Asia
external identifiers
  • other:E-ISBN 978-1-4244-6736-5
  • scopus:78650151881
ISBN
978-1-4244-6735-8
DOI
10.1109/PRIMEASIA.2010.5604927
language
English
LU publication?
yes
id
b8f427da-44dd-460d-a29f-a23b744735fe (old id 4194618)
date added to LUP
2013-12-12 10:17:20
date last changed
2017-01-01 08:01:53
@inproceedings{b8f427da-44dd-460d-a29f-a23b744735fe,
  abstract     = {PLL (Phase Locked Loop) based frequency synthesizers are widely used in the wireless communication field. This paper puts focus on the design and implementation of a 60dB SNR (Signal to Noise Ratio) FM transmitter, which realizes direct frequency modulation of audio signal by utilizing a carrier frequency ranging from 78MHz to 108MHz, with a 100 kHz channel selection resolution. Fabricated in standard 0.35μm CMOS technology, this PLL's core circuit takes an area of 745×700 μm2. The transmitter has a total power consumption of below 56mW for a 3V supply, and the strongest measured spur is below -50dBc.},
  author       = {Lu, Yan and Huo, Yiming and Wernehag, Johan and Sjöland, Henrik},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-1-4244-6735-8},
  language     = {eng},
  pages        = {202--205},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A low noise PLL based FM audio transmitter in 0.35 μm CMOS technology},
  url          = {http://dx.doi.org/10.1109/PRIMEASIA.2010.5604927},
  year         = {2010},
}