A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS
(2013) NORCHIP Conference, 2013- Abstract
- A order 3-bit continuous-time (CT) ΔΣ ADC is presented in this paper. The design equations starting from a discrete-time reference modulator to the circuit implementation are given. The non-return to zero (NRZ) DAC pulses have a half clock cycle loopdelay which is corrected by the feedforward (also known as PI) loop delay compensation, and nonlinearities in the DACs are suppressed by data-weighted averaging. The fabricated 130nm design operates at 31.25/125MHz at a power consumption of 6.04/6.32mA from a 1.2V supply, and achieves an SNDR of 64/59dB at an OSR of 32, resulting in an FOM of 5.73/2.67pJ/cony. step.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4245405
- author
- Yan, Shubo ; Andersson, Mattias LU and Sjöland, Henrik LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- NORCHIP Conference, 2013
- conference location
- Vilnius, Lithuania
- conference dates
- 2013-11-11 - 2013-11-12
- external identifiers
-
- scopus:84893570242
- ISBN
- 978-1-4799-1647-4
- DOI
- 10.1109/NORCHIP.2013.6702021
- language
- English
- LU publication?
- yes
- id
- f85b52eb-e63b-4ac2-ba60-f1c6b8121e60 (old id 4245405)
- date added to LUP
- 2016-04-04 10:08:02
- date last changed
- 2024-01-12 18:58:53
@inproceedings{f85b52eb-e63b-4ac2-ba60-f1c6b8121e60, abstract = {{A order 3-bit continuous-time (CT) ΔΣ ADC is presented in this paper. The design equations starting from a discrete-time reference modulator to the circuit implementation are given. The non-return to zero (NRZ) DAC pulses have a half clock cycle loopdelay which is corrected by the feedforward (also known as PI) loop delay compensation, and nonlinearities in the DACs are suppressed by data-weighted averaging. The fabricated 130nm design operates at 31.25/125MHz at a power consumption of 6.04/6.32mA from a 1.2V supply, and achieves an SNDR of 64/59dB at an OSR of 32, resulting in an FOM of 5.73/2.67pJ/cony. step.}}, author = {{Yan, Shubo and Andersson, Mattias and Sjöland, Henrik}}, booktitle = {{[Host publication title missing]}}, isbn = {{978-1-4799-1647-4}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS}}, url = {{http://dx.doi.org/10.1109/NORCHIP.2013.6702021}}, doi = {{10.1109/NORCHIP.2013.6702021}}, year = {{2013}}, }