Instruction Selection and Scheduling for DSP Kernels
(2014) In Microprocessors and Microsystems 38(8). p.803-813- Abstract
- As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable... (More)
- As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4586660
- author
- Arslan, Mehmet Ali
LU
and Kuchcinski, Krzysztof
LU
- organization
- publishing date
- 2014
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Instruction selection, Scheduling, Custom architecture, VLIW, Constraint programming
- in
- Microprocessors and Microsystems
- volume
- 38
- issue
- 8
- pages
- 803 - 813
- publisher
- Elsevier
- external identifiers
-
- wos:000347755200007
- scopus:84910608322
- ISSN
- 0141-9331
- DOI
- 10.1016/j.micpro.2014.04.004
- project
- High Performance Embedded Computing
- language
- English
- LU publication?
- yes
- id
- facbb018-7866-4c40-b9d4-585805292431 (old id 4586660)
- alternative location
- http://dx.doi.org/10.1016/j.micpro.2014.04.004
- date added to LUP
- 2016-04-01 10:35:51
- date last changed
- 2022-01-26 00:45:11
@article{facbb018-7866-4c40-b9d4-585805292431, abstract = {{As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation.}}, author = {{Arslan, Mehmet Ali and Kuchcinski, Krzysztof}}, issn = {{0141-9331}}, keywords = {{Instruction selection; Scheduling; Custom architecture; VLIW; Constraint programming}}, language = {{eng}}, number = {{8}}, pages = {{803--813}}, publisher = {{Elsevier}}, series = {{Microprocessors and Microsystems}}, title = {{Instruction Selection and Scheduling for DSP Kernels}}, url = {{http://dx.doi.org/10.1016/j.micpro.2014.04.004}}, doi = {{10.1016/j.micpro.2014.04.004}}, volume = {{38}}, year = {{2014}}, }