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ASIC Implementation of a Delayless Acoustic Echo Canceller: Architecture and Arithmetic

Berkeman, Anders LU (2002) 32.
Abstract
Application specific digital signal processors are superior compared to standard digital signal processors in a number of application fields, mainly due to high throughput and low power consumption traded for flexibility. This thesis deals with two areas related to hardware implementation of custom digital signal processors: design methodology and efficient implementation of arithmetic circuits. A delayless acoustic echo canceller is chosen as an example algorithm for custom hardware implementation. The canceller algorithm with no signal path delay is suitable in telecommunication applications, and has a high implementation complexity both in number of operations per second and in the variety of signal processing elements it is composed... (More)
Application specific digital signal processors are superior compared to standard digital signal processors in a number of application fields, mainly due to high throughput and low power consumption traded for flexibility. This thesis deals with two areas related to hardware implementation of custom digital signal processors: design methodology and efficient implementation of arithmetic circuits. A delayless acoustic echo canceller is chosen as an example algorithm for custom hardware implementation. The canceller algorithm with no signal path delay is suitable in telecommunication applications, and has a high implementation complexity both in number of operations per second and in the variety of signal processing elements it is composed of. The design methodology developed and applied during the echo canceller hardware implementation is presented together with a number of optimizations applicable to the algorithm, architecture, and arithmetic design levels. The work on digital arithmetic circuits includes efficient implementation of dividers and complex multipliers. A configurable divider architecture for use in a wide range of applications is proposed. The divider is based on digit recurrence algorithms. A parameterized complex multiplier designed for low power consumption and high throughput applications is presented. The multiplier is based on distributed arithmetic, offset binary coding, and adder trees. Furthermore, an arithmetic co-optimization between two algorithms, the fast Fourier transform and the FIR filter, is proposed. The acoustic echo canceller chip has been fabricated and verified for functionality, throughput, and power consumption. (Less)
Please use this url to cite or link to this publication:
author
opponent
  • Prof Wanhammar, Lars
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Signal processing, Signalbehandling, Digital Arithmetic, Acoustic Echo Cancellation, Hardware Implementation, Digital ASIC Design, Digital Signal Processing
volume
32
pages
191 pages
publisher
Department of Electroscience, Lund University
defense location
E:1406
defense date
2002-12-06 10:15
ISSN
1402-8662
ISBN
91-628-5463-1
language
English
LU publication?
yes
id
3ea5836b-e441-4e87-ac6e-7845832f3f1c (old id 465276)
date added to LUP
2007-09-06 12:47:25
date last changed
2016-09-19 08:44:54
@phdthesis{3ea5836b-e441-4e87-ac6e-7845832f3f1c,
  abstract     = {Application specific digital signal processors are superior compared to standard digital signal processors in a number of application fields, mainly due to high throughput and low power consumption traded for flexibility. This thesis deals with two areas related to hardware implementation of custom digital signal processors: design methodology and efficient implementation of arithmetic circuits. A delayless acoustic echo canceller is chosen as an example algorithm for custom hardware implementation. The canceller algorithm with no signal path delay is suitable in telecommunication applications, and has a high implementation complexity both in number of operations per second and in the variety of signal processing elements it is composed of. The design methodology developed and applied during the echo canceller hardware implementation is presented together with a number of optimizations applicable to the algorithm, architecture, and arithmetic design levels. The work on digital arithmetic circuits includes efficient implementation of dividers and complex multipliers. A configurable divider architecture for use in a wide range of applications is proposed. The divider is based on digit recurrence algorithms. A parameterized complex multiplier designed for low power consumption and high throughput applications is presented. The multiplier is based on distributed arithmetic, offset binary coding, and adder trees. Furthermore, an arithmetic co-optimization between two algorithms, the fast Fourier transform and the FIR filter, is proposed. The acoustic echo canceller chip has been fabricated and verified for functionality, throughput, and power consumption.},
  author       = {Berkeman, Anders},
  isbn         = {91-628-5463-1},
  issn         = {1402-8662},
  keyword      = {Signal processing,Signalbehandling,Digital Arithmetic,Acoustic Echo Cancellation,Hardware Implementation,Digital ASIC Design,Digital Signal Processing},
  language     = {eng},
  pages        = {191},
  publisher    = {Department of Electroscience, Lund University},
  school       = {Lund University},
  title        = {ASIC Implementation of a Delayless Acoustic Echo Canceller: Architecture and Arithmetic},
  volume       = {32},
  year         = {2002},
}