Constraint-Driven Design Space Exploration for Memory-Dominated Embedded Systems
(2004)- Abstract
- Today, embedded systems often consist of many different processing, communication, and memory units. This makes an embedded system a multiprocessor system. There are usually many possible multiprocessor architectures and therefore we need tool support for fast evaluation of numerous design alternatives. However, there is a lack of this type of tools which is partially caused by the inherent complexity of the design process. On the other hand, most designers do not have enough confidence to use and trust such tools, since the designer interaction with a tool is usually strongly limited.
The special concern in this work are memory constraints. This is motivated by the fact that memory is a dominant factor in current... (More) - Today, embedded systems often consist of many different processing, communication, and memory units. This makes an embedded system a multiprocessor system. There are usually many possible multiprocessor architectures and therefore we need tool support for fast evaluation of numerous design alternatives. However, there is a lack of this type of tools which is partially caused by the inherent complexity of the design process. On the other hand, most designers do not have enough confidence to use and trust such tools, since the designer interaction with a tool is usually strongly limited.
The special concern in this work are memory constraints. This is motivated by the fact that memory is a dominant factor in current designs. The memory influences the performance of embedded systems as well as their energy consumption. There are different types of optimizations which can improve memory utilization. Design space exploration can identify those designs which use memory system efficiently.
This thesis presents a framework, based on constraint programming (CP), for design space exploration. CP suits this task perfectly, since it offers means to model and solve problems with heterogeneous constraints. This framework makes it possible to refine a specification manually by a designer or automatically. The automatic refinement is done by adding constraints produced by specially designed exploration algorithms. In manual case, the designer decides the nature of the refinement constraints. Design space exploration framework provides an invaluable support. It helps to find (near)optimal designs given optimization criterion. When multi-objective criteria is specified then it provides (near) Pareto-optimal designs.
This thesis shows that despite the complexity of architecture selection, task assignment, task scheduling, data assignment, and data access scheduling problems, the designer is not left unaided. The presented formulation using a constraint framework coupled with problem specific search heuristics makes it possible to efficiently prune a huge design space. The exploration space pruning helps to find better designs within the same exploration time limit. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/467138
- author
- Szymanek, Radoslaw LU
- supervisor
- opponent
-
- Dutt, Nikil, University of California, Irvine, USA
- organization
- publishing date
- 2004
- type
- Thesis
- publication status
- published
- subject
- keywords
- systems, control, Datalogi, numerisk analys, system, kontroll, Computer science, memory, design space exploration, embedded systems, constraint programming, numerical analysis
- pages
- 143 pages
- publisher
- Computer Science, Lund University
- defense location
- Room E:1406, E-building, Lund Institute of Technology.
- defense date
- 2004-06-16 13:15:00
- ISBN
- 91-628-6106-9
- language
- English
- LU publication?
- yes
- additional info
- Article: Radoslaw Szymanek and Krzysztof Kuchcinski, "Design Space Exploration in System Level Synthesis under Memory Constraints", inProceedings of the 25th Euromicro conference, Milan, Italy, 1999. Article: Radoslaw Szymanek and Krzysztof Kuchcinski, "A Constructive Algorithm for Memory-Aware Task Assignment and Scheduling", in Proceedings of the Ninth International Symposium on Hardware/SoftwareCodesign, Copenhagen, Denmark, 2001. Article: Radoslaw Szymanek and Krzysztof Kuchcinski, "Partial Task Assignment of Task Graphs under Heterogeneous Resource Constraints", in Proceedings of the 40th Design Automation Conference, USA, Anaheim, June 2-6, 2003. Article: Radoslaw Szymanek, Francky Catthoor, and Krzysztof Kuchcinski, "Time-Energy Design Space Exploration for Multi-Layer Memory Architectures", in Proceedings of the Design, Automation and Test in Europe, France, Paris, February 16-22, 2004. Article: Radoslaw Szymanek, Francky Catthoor, and Krzysztof Kuchcinski, "Data Assignment and Access Scheduling Exploration for Multi-Layer Memory Architectures", submitted for publication.
- id
- 2ce1714c-86ca-4a10-9905-7994957afc6b (old id 467138)
- date added to LUP
- 2016-04-01 16:03:04
- date last changed
- 2021-05-05 16:31:48
@phdthesis{2ce1714c-86ca-4a10-9905-7994957afc6b,
abstract = {{Today, embedded systems often consist of many different processing, communication, and memory units. This makes an embedded system a multiprocessor system. There are usually many possible multiprocessor architectures and therefore we need tool support for fast evaluation of numerous design alternatives. However, there is a lack of this type of tools which is partially caused by the inherent complexity of the design process. On the other hand, most designers do not have enough confidence to use and trust such tools, since the designer interaction with a tool is usually strongly limited.<br/><br>
<br/><br>
The special concern in this work are memory constraints. This is motivated by the fact that memory is a dominant factor in current designs. The memory influences the performance of embedded systems as well as their energy consumption. There are different types of optimizations which can improve memory utilization. Design space exploration can identify those designs which use memory system efficiently.<br/><br>
<br/><br>
This thesis presents a framework, based on constraint programming (CP), for design space exploration. CP suits this task perfectly, since it offers means to model and solve problems with heterogeneous constraints. This framework makes it possible to refine a specification manually by a designer or automatically. The automatic refinement is done by adding constraints produced by specially designed exploration algorithms. In manual case, the designer decides the nature of the refinement constraints. Design space exploration framework provides an invaluable support. It helps to find (near)optimal designs given optimization criterion. When multi-objective criteria is specified then it provides (near) Pareto-optimal designs.<br/><br>
<br/><br>
This thesis shows that despite the complexity of architecture selection, task assignment, task scheduling, data assignment, and data access scheduling problems, the designer is not left unaided. The presented formulation using a constraint framework coupled with problem specific search heuristics makes it possible to efficiently prune a huge design space. The exploration space pruning helps to find better designs within the same exploration time limit.}},
author = {{Szymanek, Radoslaw}},
isbn = {{91-628-6106-9}},
keywords = {{systems; control; Datalogi; numerisk analys; system; kontroll; Computer science; memory; design space exploration; embedded systems; constraint programming; numerical analysis}},
language = {{eng}},
publisher = {{Computer Science, Lund University}},
school = {{Lund University}},
title = {{Constraint-Driven Design Space Exploration for Memory-Dominated Embedded Systems}},
year = {{2004}},
}