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Implementation of a Novel Architecture for DFT-based Channel Estimators in OFDM Systems

Stala, Michal LU ; Edfors, Ove LU and Öwall, Viktor LU (2014) SIPS 2014 In [Host publication title missing]
Abstract
A new architecture for Discrete Fourier Transform (DFT) based channel estimation has been analyzed, implemented and synthesized for ASIC. The core concept of the proposed esti- mation algorithm is to process the channel increments rather than the channel coefficients. With strong enough time correlation, we can reduce the wordlength of processing blocks compared to standard channel estimators and hence the resulting area and power. We provide an analytical tool to predict the potential gains in bit reduction for different mobility scenarios. Our simulations show that the wordlength can be reduced from 9 to 3 bits when operating in low mobility scenarios, with 5Hz Doppler frequency, while maintaining acceptable performance. Synthesis... (More)
A new architecture for Discrete Fourier Transform (DFT) based channel estimation has been analyzed, implemented and synthesized for ASIC. The core concept of the proposed esti- mation algorithm is to process the channel increments rather than the channel coefficients. With strong enough time correlation, we can reduce the wordlength of processing blocks compared to standard channel estimators and hence the resulting area and power. We provide an analytical tool to predict the potential gains in bit reduction for different mobility scenarios. Our simulations show that the wordlength can be reduced from 9 to 3 bits when operating in low mobility scenarios, with 5Hz Doppler frequency, while maintaining acceptable performance. Synthesis results show up to 40% reduction in area, compared to the original DFT-based approach, in a 65nm CMOS process. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
SIPS 2014
external identifiers
  • scopus:84920281236
language
English
LU publication?
yes
id
551181af-b12b-4b0a-9816-b5918e74e7a0 (old id 4699344)
date added to LUP
2014-10-22 15:07:18
date last changed
2017-01-01 08:03:07
@inproceedings{551181af-b12b-4b0a-9816-b5918e74e7a0,
  abstract     = {A new architecture for Discrete Fourier Transform (DFT) based channel estimation has been analyzed, implemented and synthesized for ASIC. The core concept of the proposed esti- mation algorithm is to process the channel increments rather than the channel coefficients. With strong enough time correlation, we can reduce the wordlength of processing blocks compared to standard channel estimators and hence the resulting area and power. We provide an analytical tool to predict the potential gains in bit reduction for different mobility scenarios. Our simulations show that the wordlength can be reduced from 9 to 3 bits when operating in low mobility scenarios, with 5Hz Doppler frequency, while maintaining acceptable performance. Synthesis results show up to 40% reduction in area, compared to the original DFT-based approach, in a 65nm CMOS process.},
  author       = {Stala, Michal and Edfors, Ove and Öwall, Viktor},
  booktitle    = {[Host publication title missing]},
  language     = {eng},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Implementation of a Novel Architecture for DFT-based Channel Estimators in OFDM Systems},
  year         = {2014},
}