Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers
Liu, Liang LU
(2014)
In IEEE Transactions on Circuits and Systems Part 1: Regular Papers
61(8).
p.2422-2432
- Abstract
- This paper presents the VLSI design of an energy-efficient, high-throughput soft-input soft-output signal detector for iterative multiple-input multiple-output (MIMO) receiver. The detector is evolved from our previously developed imbalanced fixed complexity sphere decoder and adopts several new algorithm-level techniques to exploit the available a priori information of transmitted bits. More specifically, an adaptive tree-travel control scheme, a reliability-dependent log-likelihood ratio correction method and an iteration-based hybrid node enumeration technique are proposed to provide near-optimal detection performance with much reduced computational complexity. A multi-stage parallel VLSI architecture is developed to implement the... (More)
- This paper presents the VLSI design of an energy-efficient, high-throughput soft-input soft-output signal detector for iterative multiple-input multiple-output (MIMO) receiver. The detector is evolved from our previously developed imbalanced fixed complexity sphere decoder and adopts several new algorithm-level techniques to exploit the available a priori information of transmitted bits. More specifically, an adaptive tree-travel control scheme, a reliability-dependent log-likelihood ratio correction method and an iteration-based hybrid node enumeration technique are proposed to provide near-optimal detection performance with much reduced computational complexity. A multi-stage parallel VLSI architecture is developed to implement the proposed algorithm with high detection throughput. Furthermore, the block-level clock gating is deployed to save power when the tree-search space is reduced, while still preserving the constant-throughput feature. As a proof of concept, we designed the iterative detector using a 65-nm CMOS technology and conducted post-layout simulation. The core area is 0.64 mm(2) with 198.2 k gates. Working at 240-MHz clock frequency with 1.0-V voltage supply, the detector achieves a maximum 1.44-Gbps throughput. Under frequency-selective channels, the detector core consumes 98.5-, 127.9-, and 149.5-pJ energy per bit detection in open-loop, 2-iteration, and 4-iteration modes, respectively. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4712969
- author
- Liu, Liang
LU
- organization
- publishing date
- 2014
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Energy efficient, multiple-input multiple-output (MIMO), signal, detector, soft-input soft-output (SISO), very-large scale integration, (VLSI)
- in
- IEEE Transactions on Circuits and Systems Part 1: Regular Papers
- volume
- 61
- issue
- 8
- pages
- 2422 - 2432
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000341593000023
- scopus:84905407026
- ISSN
- 1549-8328
- DOI
- 10.1109/TCSI.2014.2304657
- language
- English
- LU publication?
- yes
- id
- 7140e9f1-96c4-461b-bc14-83412ec0d67b (old id 4712969)
- date added to LUP
- 2016-04-01 10:42:19
- date last changed
- 2024-01-06 23:05:29
@article{7140e9f1-96c4-461b-bc14-83412ec0d67b,
abstract = {{This paper presents the VLSI design of an energy-efficient, high-throughput soft-input soft-output signal detector for iterative multiple-input multiple-output (MIMO) receiver. The detector is evolved from our previously developed imbalanced fixed complexity sphere decoder and adopts several new algorithm-level techniques to exploit the available a priori information of transmitted bits. More specifically, an adaptive tree-travel control scheme, a reliability-dependent log-likelihood ratio correction method and an iteration-based hybrid node enumeration technique are proposed to provide near-optimal detection performance with much reduced computational complexity. A multi-stage parallel VLSI architecture is developed to implement the proposed algorithm with high detection throughput. Furthermore, the block-level clock gating is deployed to save power when the tree-search space is reduced, while still preserving the constant-throughput feature. As a proof of concept, we designed the iterative detector using a 65-nm CMOS technology and conducted post-layout simulation. The core area is 0.64 mm(2) with 198.2 k gates. Working at 240-MHz clock frequency with 1.0-V voltage supply, the detector achieves a maximum 1.44-Gbps throughput. Under frequency-selective channels, the detector core consumes 98.5-, 127.9-, and 149.5-pJ energy per bit detection in open-loop, 2-iteration, and 4-iteration modes, respectively.}},
author = {{Liu, Liang}},
issn = {{1549-8328}},
keywords = {{Energy efficient; multiple-input multiple-output (MIMO); signal; detector; soft-input soft-output (SISO); very-large scale integration; (VLSI)}},
language = {{eng}},
number = {{8}},
pages = {{2422--2432}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Circuits and Systems Part 1: Regular Papers}},
title = {{Energy-Efficient Soft-Input Soft-Output Signal Detector for Iterative MIMO Receivers}},
url = {{http://dx.doi.org/10.1109/TCSI.2014.2304657}},
doi = {{10.1109/TCSI.2014.2304657}},
volume = {{61}},
year = {{2014}},
}