A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio
(2015) 32nd NORCHIP Conference, 2014- Abstract
- A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4731271
- author
- Wang, Ji ; Carmona, Manuel Bejarano ; Hall, Helgi ; Radjen, Dejan LU and Lu, Ping LU
- organization
- publishing date
- 2015
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2014 NORCHIP
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 32nd NORCHIP Conference, 2014
- conference location
- Tampere, Finland
- conference dates
- 2014-10-27 - 2014-10-28
- external identifiers
-
- scopus:84921479840
- ISBN
- 978-1-4799-5442-1
- DOI
- 10.1109/NORCHIP.2014.7004720
- language
- English
- LU publication?
- yes
- id
- 40fad83c-e9e0-4af8-a1f8-f873789e16cf (old id 4731271)
- date added to LUP
- 2016-04-04 14:27:54
- date last changed
- 2022-04-27 01:09:38
@inproceedings{40fad83c-e9e0-4af8-a1f8-f873789e16cf, abstract = {{A 9-bit 1-MS/s successive-approximation (SAR) analog-to-digital converter (ADC) for ultra low power radio applications using 130 nm CMOS is presented. The ADC achieves a power consumption of 7/μW according to simulation results. This ultra low power is realized by employing a maximally simplified ADC architecture that consists of a dynamic latch comparator, a charge redistribution digital-to-analog converter (DAC), and a SAR logic block based on transmission gate flip-flops. Working at a supply voltage of 0.8 V, the SAR ADC achieves a FOM of 15 fJ/conversion.}}, author = {{Wang, Ji and Carmona, Manuel Bejarano and Hall, Helgi and Radjen, Dejan and Lu, Ping}}, booktitle = {{2014 NORCHIP}}, isbn = {{978-1-4799-5442-1}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio}}, url = {{http://dx.doi.org/10.1109/NORCHIP.2014.7004720}}, doi = {{10.1109/NORCHIP.2014.7004720}}, year = {{2015}}, }