Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
(2010) In Microprocessors and Microsystems 34(2010). p.129-137- Abstract
- This paper discusses design and measurements of a flexible Viterbi decoder
fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing
various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1486157
- author
- Kamuf, Matthias ; Rodrigues, Joachim LU ; Anderson, John B LU and Öwall, Viktor LU
- organization
- publishing date
- 2010
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Microprocessors and Microsystems
- volume
- 34
- issue
- 2010
- pages
- 129 - 137
- publisher
- Elsevier
- external identifiers
-
- wos:000278730500003
- scopus:77955224568
- ISSN
- 0141-9331
- DOI
- 10.1016/j.micpro.2009.09.004
- project
- PCC: Algorithm and Hardware
- language
- English
- LU publication?
- yes
- id
- 49f07dc1-dd57-45bd-87dc-da2fe3f31319 (old id 1486157)
- date added to LUP
- 2016-04-01 09:54:00
- date last changed
- 2022-01-25 17:47:12
@article{49f07dc1-dd57-45bd-87dc-da2fe3f31319, abstract = {{This paper discusses design and measurements of a flexible Viterbi decoder<br/><br> fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing<br/><br> various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.}}, author = {{Kamuf, Matthias and Rodrigues, Joachim and Anderson, John B and Öwall, Viktor}}, issn = {{0141-9331}}, language = {{eng}}, number = {{2010}}, pages = {{129--137}}, publisher = {{Elsevier}}, series = {{Microprocessors and Microsystems}}, title = {{Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS}}, url = {{https://lup.lub.lu.se/search/files/1369335/1738115.pdf}}, doi = {{10.1016/j.micpro.2009.09.004}}, volume = {{34}}, year = {{2010}}, }