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A carbon nanotube gated carbon nanotube transistor with 5 ps gate delay

Svensson, J. LU ; Tarakanov, Yu ; Lee, D. S. ; Kinaret, J. M. ; Park, Y. W. and Campbell, E. E.B. LU (2008) In Nanotechnology 19(32).
Abstract

Semiconducting carbon nanotubes (CNTs) are attractive as channel material for field-effect transistors due to their high carrier mobility. In this paper we show that a local CNT gate can provide a significant improvement in the subthreshold slope of a CNT transistor compared to back gate switching and provide gate delays as low as 5 ps. The CNT gated CNT transistor devices are fabricated using a two-step chemical vapour deposition technique. The measured transfer characteristics are in very good agreement with theoretical modelling results that provide confirmation of the operating principle of the transistors. Gate delays below 2 ps should be readily achievable by reducing the thickness of the gate dielectric.

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author
; ; ; ; and
publishing date
type
Contribution to journal
publication status
published
subject
in
Nanotechnology
volume
19
issue
32
article number
325201
publisher
IOP Publishing
external identifiers
  • scopus:47249097841
ISSN
0957-4484
DOI
10.1088/0957-4484/19/32/325201
language
English
LU publication?
no
id
4b0a4070-163e-4c23-82b4-f9659cdcce9c
date added to LUP
2020-05-05 12:16:07
date last changed
2022-03-11 00:50:39
@article{4b0a4070-163e-4c23-82b4-f9659cdcce9c,
  abstract     = {{<p>Semiconducting carbon nanotubes (CNTs) are attractive as channel material for field-effect transistors due to their high carrier mobility. In this paper we show that a local CNT gate can provide a significant improvement in the subthreshold slope of a CNT transistor compared to back gate switching and provide gate delays as low as 5 ps. The CNT gated CNT transistor devices are fabricated using a two-step chemical vapour deposition technique. The measured transfer characteristics are in very good agreement with theoretical modelling results that provide confirmation of the operating principle of the transistors. Gate delays below 2 ps should be readily achievable by reducing the thickness of the gate dielectric.</p>}},
  author       = {{Svensson, J. and Tarakanov, Yu and Lee, D. S. and Kinaret, J. M. and Park, Y. W. and Campbell, E. E.B.}},
  issn         = {{0957-4484}},
  language     = {{eng}},
  month        = {{08}},
  number       = {{32}},
  publisher    = {{IOP Publishing}},
  series       = {{Nanotechnology}},
  title        = {{A carbon nanotube gated carbon nanotube transistor with 5 ps gate delay}},
  url          = {{http://dx.doi.org/10.1088/0957-4484/19/32/325201}},
  doi          = {{10.1088/0957-4484/19/32/325201}},
  volume       = {{19}},
  year         = {{2008}},
}