Energy Efficient Group-Sort QRD Processor with On-line Update for MIMO Channel Pre-processing
(2015) In IEEE Transactions on Circuits and Systems Part 1: Regular Papers 62(5). p.1220-1229- Abstract
- This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, between the traditional brute-force SQRD and a proposed group-sort QR update strategy. A reconfigurable vector processor is accordingly developed to support the adaptive processing with high hardware efficiency. Furthermore, on-chip power management technique is also integrated to obtain real-time power-saving by adapting the voltage supply based on the... (More)
- This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, between the traditional brute-force SQRD and a proposed group-sort QR update strategy. A reconfigurable vector processor is accordingly developed to support the adaptive processing with high hardware efficiency. Furthermore, on-chip power management technique is also integrated to obtain real-time power-saving by adapting the voltage supply based on the instantaneous workload. As a proof-of-concept, we implemented the processor using a 65nm CMOS technology and conducted post-layout simulation. The proposed SQRD processor occupies 0.71mm2 core area and has a throughput of up to 69MQRD/s. Compared to the brute-force approach, an energy reduction of 10~61.8% is achieved. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/5050000
- author
- Zhang, Chenxin LU ; Prabhu, Hemanth LU ; Liu, Yangxurui LU ; Liu, Liang LU ; Edfors, Ove LU and Öwall, Viktor LU
- organization
- publishing date
- 2015
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- QR decomposition, sorting, channel preprocessing, MIMO, reconfigurable processor
- in
- IEEE Transactions on Circuits and Systems Part 1: Regular Papers
- volume
- 62
- issue
- 5
- pages
- 1220 - 1229
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000353887300002
- scopus:85027939515
- ISSN
- 1549-8328
- DOI
- 10.1109/TCSI.2015.2402936
- project
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
- language
- English
- LU publication?
- yes
- id
- 369f2da4-a364-4a80-a65d-170e1db3816d (old id 5050000)
- date added to LUP
- 2016-04-01 10:23:36
- date last changed
- 2024-01-06 15:32:55
@article{369f2da4-a364-4a80-a65d-170e1db3816d, abstract = {{This paper presents a Sorted QR-Decomposition (SQRD) processor for 3GPP LTE-A system. It achieves energy efficiency by co-optimizing techniques, such as heterogeneous processing, reconfigurable architecture, and dual-supply voltage operation. At algorithm level, a low-complexity hybrid decomposition scheme is adopted, which switches, depending on the energy distribution of spatial channels, between the traditional brute-force SQRD and a proposed group-sort QR update strategy. A reconfigurable vector processor is accordingly developed to support the adaptive processing with high hardware efficiency. Furthermore, on-chip power management technique is also integrated to obtain real-time power-saving by adapting the voltage supply based on the instantaneous workload. As a proof-of-concept, we implemented the processor using a 65nm CMOS technology and conducted post-layout simulation. The proposed SQRD processor occupies 0.71mm2 core area and has a throughput of up to 69MQRD/s. Compared to the brute-force approach, an energy reduction of 10~61.8% is achieved.}}, author = {{Zhang, Chenxin and Prabhu, Hemanth and Liu, Yangxurui and Liu, Liang and Edfors, Ove and Öwall, Viktor}}, issn = {{1549-8328}}, keywords = {{QR decomposition; sorting; channel preprocessing; MIMO; reconfigurable processor}}, language = {{eng}}, number = {{5}}, pages = {{1220--1229}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Transactions on Circuits and Systems Part 1: Regular Papers}}, title = {{Energy Efficient Group-Sort QRD Processor with On-line Update for MIMO Channel Pre-processing}}, url = {{https://lup.lub.lu.se/search/files/1805685/5469508.pdf}}, doi = {{10.1109/TCSI.2015.2402936}}, volume = {{62}}, year = {{2015}}, }