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A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL

Wu, Ying; Lu, Ping LU and Staszewski, Robert Bogdan (2015) IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015 In 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) p.95-98
Abstract
A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
pages
95 - 98
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015
external identifiers
  • Scopus:84975735384
DOI
10.1109/RFIC.2015.7337713
language
English
LU publication?
yes
id
1555f350-6496-471f-98f9-ebab25f1bc9f (old id 5101356)
date added to LUP
2015-02-24 12:22:41
date last changed
2017-01-01 08:07:46
@inproceedings{1555f350-6496-471f-98f9-ebab25f1bc9f,
  abstract     = {A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.},
  author       = {Wu, Ying and Lu, Ping and Staszewski, Robert Bogdan},
  booktitle    = { 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)},
  language     = {eng},
  pages        = {95--98},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL},
  url          = {http://dx.doi.org/10.1109/RFIC.2015.7337713},
  year         = {2015},
}