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An efficient programmable engine for interpolation of multi-standard video coding

Zhang, Zhi LU ; Yan, Xiaolang and Qin, Xing (2007) International Conference on ASIC (ASICON) In [Host publication title missing] p.750-753
Abstract
This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm2, and the frequency can achieve... (More)
This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm2, and the frequency can achieve 179.5 MHz. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
750 - 753
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
International Conference on ASIC (ASICON)
external identifiers
  • scopus:48349103759
ISBN
978-1-4244-1132-0
DOI
10.1109/ICASIC.2007.4415739
language
English
LU publication?
no
id
75b2df43-1ac3-4993-b348-0f3bf5e50c95 (old id 5147536)
date added to LUP
2015-03-04 12:27:50
date last changed
2017-01-01 08:05:51
@inproceedings{75b2df43-1ac3-4993-b348-0f3bf5e50c95,
  abstract     = {This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm2, and the frequency can achieve 179.5 MHz.},
  author       = {Zhang, Zhi and Yan, Xiaolang and Qin, Xing},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-1-4244-1132-0},
  language     = {eng},
  pages        = {750--753},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {An efficient programmable engine for interpolation of multi-standard video coding},
  url          = {http://dx.doi.org/10.1109/ICASIC.2007.4415739},
  year         = {2007},
}