An efficient programmable engine for interpolation of multi-standard video coding
(2007) International Conference on ASIC (ASICON) p.750-753- Abstract
- This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm2, and the frequency can achieve... (More)
- This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm2, and the frequency can achieve 179.5 MHz. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/5147536
- author
- Zhang, Zhi LU ; Yan, Xiaolang and Qin, Xing
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 750 - 753
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- International Conference on ASIC (ASICON)
- conference location
- Guilin, China
- conference dates
- 2007-10-22 - 2007-10-25
- external identifiers
-
- scopus:48349103759
- ISBN
- 978-1-4244-1132-0
- DOI
- 10.1109/ICASIC.2007.4415739
- language
- English
- LU publication?
- no
- id
- 75b2df43-1ac3-4993-b348-0f3bf5e50c95 (old id 5147536)
- date added to LUP
- 2016-04-04 11:54:01
- date last changed
- 2022-03-23 18:20:44
@inproceedings{75b2df43-1ac3-4993-b348-0f3bf5e50c95, abstract = {{This paper presents an efficient programmable engine that supports diverse interpolation algorithm in different video coding standards, such as H.264/AVC, and the Chinese national standard, AVS. It is a VLIW(very long instruction word) and SIMD(single instruction multiple data) hybrid architecture which could issue four ALU operations and one memory reference or a branch operation in every clock cycle, and execute four different data streams in a single instruction. An 8-bank 2-D on-chip memory is proposed to improve the parallelism of memory accessing. The design is implemented with Verilog-HDL, and synthesized with synopsys tools using 0.18 um Standard Cell Library. The total area is about 3.80 x 4.31 mm2, and the frequency can achieve 179.5 MHz.}}, author = {{Zhang, Zhi and Yan, Xiaolang and Qin, Xing}}, booktitle = {{[Host publication title missing]}}, isbn = {{978-1-4244-1132-0}}, language = {{eng}}, pages = {{750--753}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{An efficient programmable engine for interpolation of multi-standard video coding}}, url = {{http://dx.doi.org/10.1109/ICASIC.2007.4415739}}, doi = {{10.1109/ICASIC.2007.4415739}}, year = {{2007}}, }