Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
Samii, Soheil ; Larsson, Erik LU
; Chakrabarty, Krishnendu
and Peng, Zebo
(2006)
IEEE International Test Conference ITC '06
p.1-32
- Abstract
- Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in,... (More)
- Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in, launch-and-capture, and scan-out. Further, we allow a unique power model per wrapper chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be substantially reduced (on average 16.5% reduction) by using the proposed cycle-accurate test power model. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341033
- author
- Samii, Soheil
; Larsson, Erik
LU
; Chakrabarty, Krishnendu
and Peng, Zebo
- publishing date
- 2006
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, system-on-chip, test scheduling, power modelling
- host publication
- [Host publication title missing]
- pages
- 1 - 32
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Test Conference ITC '06
- conference location
- Santa Clara, CA, United States
- conference dates
- 2006-10-24 - 2006-10-26
- external identifiers
-
- scopus:39749107275
- ISSN
- 1089-3539
- ISBN
- 1-4244-0292-1
- DOI
- 10.1109/TEST.2006.297693
- language
- English
- LU publication?
- no
- id
- 596355b8-f19e-40b2-b123-6a94edb195fc (old id 2341033)
- date added to LUP
- 2016-04-01 16:50:00
- date last changed
- 2022-04-23 00:44:21
@inproceedings{596355b8-f19e-40b2-b123-6a94edb195fc,
abstract = {{Concurrent testing of the cores in a modular core-based System-on-Chip reduces the test application time but increases the test power consumption. Power models and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is pessimistic but simple for a scheduling algorithm to handle. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding scheduling algorithm. The model takes into account the switching activity in the scan chains caused by both the test stimuli and the test responses during scan-in, launch-and-capture, and scan-out. Further, we allow a unique power model per wrapper chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be substantially reduced (on average 16.5% reduction) by using the proposed cycle-accurate test power model.}},
author = {{Samii, Soheil and Larsson, Erik and Chakrabarty, Krishnendu and Peng, Zebo}},
booktitle = {{[Host publication title missing]}},
isbn = {{1-4244-0292-1}},
issn = {{1089-3539}},
keywords = {{testing; system-on-chip; test scheduling; power modelling}},
language = {{eng}},
pages = {{1--32}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling}},
url = {{http://dx.doi.org/10.1109/TEST.2006.297693}},
doi = {{10.1109/TEST.2006.297693}},
year = {{2006}},
}